cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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switch_to.h (1195B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef __ASM_ARM_SWITCH_TO_H
      3#define __ASM_ARM_SWITCH_TO_H
      4
      5#include <linux/thread_info.h>
      6#include <asm/smp_plat.h>
      7
      8/*
      9 * For v7 SMP cores running a preemptible kernel we may be pre-empted
     10 * during a TLB maintenance operation, so execute an inner-shareable dsb
     11 * to ensure that the maintenance completes in case we migrate to another
     12 * CPU.
     13 */
     14#if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
     15#define __complete_pending_tlbi()	dsb(ish)
     16#else
     17#define __complete_pending_tlbi()
     18#endif
     19
     20/*
     21 * switch_to(prev, next) should switch from task `prev' to `next'
     22 * `prev' will never be the same as `next'.  schedule() itself
     23 * contains the memory barrier to tell GCC not to cache `current'.
     24 */
     25extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
     26
     27#define switch_to(prev,next,last)					\
     28do {									\
     29	__complete_pending_tlbi();					\
     30	if (IS_ENABLED(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || is_smp())	\
     31		__this_cpu_write(__entry_task, next);			\
     32	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
     33} while (0)
     34
     35#endif /* __ASM_ARM_SWITCH_TO_H */