cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cp15.h (954B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) 2020 ARM Ltd.
      4 */
      5#ifndef __ASM_VDSO_CP15_H
      6#define __ASM_VDSO_CP15_H
      7
      8#ifndef __ASSEMBLY__
      9
     10#ifdef CONFIG_CPU_CP15
     11
     12#include <linux/stringify.h>
     13
     14#define __ACCESS_CP15(CRn, Op1, CRm, Op2)	\
     15	"mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
     16#define __ACCESS_CP15_64(Op1, CRm)		\
     17	"mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
     18
     19#define __read_sysreg(r, w, c, t) ({				\
     20	t __val;						\
     21	asm volatile(r " " c : "=r" (__val));			\
     22	__val;							\
     23})
     24#define read_sysreg(...)		__read_sysreg(__VA_ARGS__)
     25
     26#define __write_sysreg(v, r, w, c, t)	asm volatile(w " " c : : "r" ((t)(v)))
     27#define write_sysreg(v, ...)		__write_sysreg(v, __VA_ARGS__)
     28
     29#define BPIALL				__ACCESS_CP15(c7, 0, c5, 6)
     30#define ICIALLU				__ACCESS_CP15(c7, 0, c5, 0)
     31
     32#define CNTVCT				__ACCESS_CP15_64(1, c14)
     33
     34#endif /* CONFIG_CPU_CP15 */
     35
     36#endif /* __ASSEMBLY__ */
     37
     38#endif /* __ASM_VDSO_CP15_H */