cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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byteorder.h (711B)

      1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
      2/*
      3 *  arch/arm/include/asm/byteorder.h
      4 *
      5 * ARM Endian-ness.  In little endian mode, the data bus is connected such
      6 * that byte accesses appear as:
      7 *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
      8 * and word accesses (data or instruction) appear as:
      9 *  d0...d31
     10 *
     11 * When in big endian mode, byte accesses appear as:
     12 *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
     13 * and word accesses (data or instruction) appear as:
     14 *  d0...d31
     15 */
     16#ifndef __ASM_ARM_BYTEORDER_H
     17#define __ASM_ARM_BYTEORDER_H
     18
     19#ifdef __ARMEB__
     20#include <linux/byteorder/big_endian.h>
     21#else
     22#include <linux/byteorder/little_endian.h>
     23#endif
     24
     25#endif
     26