cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ptrace.h (4288B)


      1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
      2/*
      3 *  arch/arm/include/asm/ptrace.h
      4 *
      5 *  Copyright (C) 1996-2003 Russell King
      6 *
      7 * This program is free software; you can redistribute it and/or modify
      8 * it under the terms of the GNU General Public License version 2 as
      9 * published by the Free Software Foundation.
     10 */
     11#ifndef _UAPI__ASM_ARM_PTRACE_H
     12#define _UAPI__ASM_ARM_PTRACE_H
     13
     14#include <asm/hwcap.h>
     15
     16#define PTRACE_GETREGS		12
     17#define PTRACE_SETREGS		13
     18#define PTRACE_GETFPREGS	14
     19#define PTRACE_SETFPREGS	15
     20/* PTRACE_ATTACH is 16 */
     21/* PTRACE_DETACH is 17 */
     22#define PTRACE_GETWMMXREGS	18
     23#define PTRACE_SETWMMXREGS	19
     24/* 20 is unused */
     25#define PTRACE_OLDSETOPTIONS	21
     26#define PTRACE_GET_THREAD_AREA	22
     27#define PTRACE_SET_SYSCALL	23
     28/* PTRACE_SYSCALL is 24 */
     29#define PTRACE_GETCRUNCHREGS	25 /* obsolete */
     30#define PTRACE_SETCRUNCHREGS	26 /* obsolete */
     31#define PTRACE_GETVFPREGS	27
     32#define PTRACE_SETVFPREGS	28
     33#define PTRACE_GETHBPREGS	29
     34#define PTRACE_SETHBPREGS	30
     35#define PTRACE_GETFDPIC		31
     36
     37#define PTRACE_GETFDPIC_EXEC	0
     38#define PTRACE_GETFDPIC_INTERP	1
     39
     40/*
     41 * PSR bits
     42 * Note on V7M there is no mode contained in the PSR
     43 */
     44#define USR26_MODE	0x00000000
     45#define FIQ26_MODE	0x00000001
     46#define IRQ26_MODE	0x00000002
     47#define SVC26_MODE	0x00000003
     48#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
     49/*
     50 * Use 0 here to get code right that creates a userspace
     51 * or kernel space thread.
     52 */
     53#define USR_MODE	0x00000000
     54#define SVC_MODE	0x00000000
     55#else
     56#define USR_MODE	0x00000010
     57#define SVC_MODE	0x00000013
     58#endif
     59#define FIQ_MODE	0x00000011
     60#define IRQ_MODE	0x00000012
     61#define MON_MODE	0x00000016
     62#define ABT_MODE	0x00000017
     63#define HYP_MODE	0x0000001a
     64#define UND_MODE	0x0000001b
     65#define SYSTEM_MODE	0x0000001f
     66#define MODE32_BIT	0x00000010
     67#define MODE_MASK	0x0000001f
     68
     69#define V4_PSR_T_BIT	0x00000020	/* >= V4T, but not V7M */
     70#define V7M_PSR_T_BIT	0x01000000
     71#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
     72#define PSR_T_BIT	V7M_PSR_T_BIT
     73#else
     74/* for compatibility */
     75#define PSR_T_BIT	V4_PSR_T_BIT
     76#endif
     77
     78#define PSR_F_BIT	0x00000040	/* >= V4, but not V7M */
     79#define PSR_I_BIT	0x00000080	/* >= V4, but not V7M */
     80#define PSR_A_BIT	0x00000100	/* >= V6, but not V7M */
     81#define PSR_E_BIT	0x00000200	/* >= V6, but not V7M */
     82#define PSR_J_BIT	0x01000000	/* >= V5J, but not V7M */
     83#define PSR_Q_BIT	0x08000000	/* >= V5E, including V7M */
     84#define PSR_V_BIT	0x10000000
     85#define PSR_C_BIT	0x20000000
     86#define PSR_Z_BIT	0x40000000
     87#define PSR_N_BIT	0x80000000
     88
     89/*
     90 * Groups of PSR bits
     91 */
     92#define PSR_f		0xff000000	/* Flags		*/
     93#define PSR_s		0x00ff0000	/* Status		*/
     94#define PSR_x		0x0000ff00	/* Extension		*/
     95#define PSR_c		0x000000ff	/* Control		*/
     96
     97/*
     98 * ARMv7 groups of PSR bits
     99 */
    100#define APSR_MASK	0xf80f0000	/* N, Z, C, V, Q and GE flags */
    101#define PSR_ISET_MASK	0x01000010	/* ISA state (J, T) mask */
    102#define PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */
    103#define PSR_ENDIAN_MASK	0x00000200	/* Endianness state mask */
    104
    105/*
    106 * Default endianness state
    107 */
    108#ifdef CONFIG_CPU_ENDIAN_BE8
    109#define PSR_ENDSTATE	PSR_E_BIT
    110#else
    111#define PSR_ENDSTATE	0
    112#endif
    113
    114/* 
    115 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
    116 * process is located in memory.
    117 */
    118#define PT_TEXT_ADDR		0x10000
    119#define PT_DATA_ADDR		0x10004
    120#define PT_TEXT_END_ADDR	0x10008
    121
    122#ifndef __ASSEMBLY__
    123
    124/*
    125 * This struct defines the way the registers are stored on the
    126 * stack during a system call.  Note that sizeof(struct pt_regs)
    127 * has to be a multiple of 8.
    128 */
    129#ifndef __KERNEL__
    130struct pt_regs {
    131	long uregs[18];
    132};
    133#endif /* __KERNEL__ */
    134
    135#define ARM_cpsr	uregs[16]
    136#define ARM_pc		uregs[15]
    137#define ARM_lr		uregs[14]
    138#define ARM_sp		uregs[13]
    139#define ARM_ip		uregs[12]
    140#define ARM_fp		uregs[11]
    141#define ARM_r10		uregs[10]
    142#define ARM_r9		uregs[9]
    143#define ARM_r8		uregs[8]
    144#define ARM_r7		uregs[7]
    145#define ARM_r6		uregs[6]
    146#define ARM_r5		uregs[5]
    147#define ARM_r4		uregs[4]
    148#define ARM_r3		uregs[3]
    149#define ARM_r2		uregs[2]
    150#define ARM_r1		uregs[1]
    151#define ARM_r0		uregs[0]
    152#define ARM_ORIG_r0	uregs[17]
    153
    154/*
    155 * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
    156 * and core dumps.
    157 */
    158#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )
    159
    160
    161#endif /* __ASSEMBLY__ */
    162
    163#endif /* _UAPI__ASM_ARM_PTRACE_H */