cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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swab.h (1460B)


      1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
      2/*
      3 *  arch/arm/include/asm/byteorder.h
      4 *
      5 * ARM Endian-ness.  In little endian mode, the data bus is connected such
      6 * that byte accesses appear as:
      7 *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
      8 * and word accesses (data or instruction) appear as:
      9 *  d0...d31
     10 *
     11 * When in big endian mode, byte accesses appear as:
     12 *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
     13 * and word accesses (data or instruction) appear as:
     14 *  d0...d31
     15 */
     16#ifndef _UAPI__ASM_ARM_SWAB_H
     17#define _UAPI__ASM_ARM_SWAB_H
     18
     19#include <linux/compiler.h>
     20#include <linux/types.h>
     21
     22#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
     23#  define __SWAB_64_THRU_32__
     24#endif
     25
     26
     27#if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6
     28static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
     29{
     30	__u32 t;
     31
     32#ifndef __thumb__
     33	if (!__builtin_constant_p(x)) {
     34		/*
     35		 * The compiler needs a bit of a hint here to always do the
     36		 * right thing and not screw it up to different degrees
     37		 * depending on the gcc version.
     38		 */
     39		asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
     40	} else
     41#endif
     42		t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
     43
     44	x = (x << 24) | (x >> 8);		/* mov r0,r0,ror #8      */
     45	t &= ~0x00FF0000;			/* bic r1,r1,#0x00FF0000 */
     46	x ^= (t >> 8);				/* eor r0,r0,r1,lsr #8   */
     47
     48	return x;
     49}
     50#define __arch_swab32 __arch_swab32
     51
     52#endif
     53
     54#endif /* _UAPI__ASM_ARM_SWAB_H */