cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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delay-loop.S (1063B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  linux/arch/arm/lib/delay.S
      4 *
      5 *  Copyright (C) 1995, 1996 Russell King
      6 */
      7#include <linux/linkage.h>
      8#include <asm/assembler.h>
      9#include <asm/delay.h>
     10
     11		.text
     12
     13.LC0:		.word	loops_per_jiffy
     14.LC1:		.word	UDELAY_MULT
     15
     16/*
     17 * loops = r0 * HZ * loops_per_jiffy / 1000000
     18 *
     19 * r0  <= 2000
     20 * HZ  <= 1000
     21 */
     22
     23ENTRY(__loop_udelay)
     24		ldr	r2, .LC1
     25		mul	r0, r2, r0		@ r0 = delay_us * UDELAY_MULT
     26ENTRY(__loop_const_udelay)			@ 0 <= r0 <= 0xfffffaf0
     27		ldr	r2, .LC0
     28		ldr	r2, [r2]
     29		umull	r1, r0, r2, r0		@ r0-r1 = r0 * loops_per_jiffy
     30		adds	r1, r1, #0xffffffff	@ rounding up ...
     31		adcs	r0, r0, r0		@ and right shift by 31
     32		reteq	lr
     33
     34		.align 3
     35
     36@ Delay routine
     37ENTRY(__loop_delay)
     38		subs	r0, r0, #1
     39#if 0
     40		retls	lr
     41		subs	r0, r0, #1
     42		retls	lr
     43		subs	r0, r0, #1
     44		retls	lr
     45		subs	r0, r0, #1
     46		retls	lr
     47		subs	r0, r0, #1
     48		retls	lr
     49		subs	r0, r0, #1
     50		retls	lr
     51		subs	r0, r0, #1
     52		retls	lr
     53		subs	r0, r0, #1
     54#endif
     55		bhi	__loop_delay
     56		ret	lr
     57ENDPROC(__loop_udelay)
     58ENDPROC(__loop_const_udelay)
     59ENDPROC(__loop_delay)