cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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io-writesl.S (1120B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  linux/arch/arm/lib/io-writesl.S
      4 *
      5 *  Copyright (C) 1995-2000 Russell King
      6 */
      7#include <linux/linkage.h>
      8#include <asm/assembler.h>
      9
     10ENTRY(__raw_writesl)
     11		teq	r2, #0		@ do we have to check for the zero len?
     12		reteq	lr
     13		ands	ip, r1, #3
     14		bne	3f
     15
     16		subs	r2, r2, #4
     17		bmi	2f
     18		stmfd	sp!, {r4, lr}
     191:		ldmia	r1!, {r3, r4, ip, lr}
     20		subs	r2, r2, #4
     21		str	r3, [r0, #0]
     22		str	r4, [r0, #0]
     23		str	ip, [r0, #0]
     24		str	lr, [r0, #0]
     25		bpl	1b
     26		ldmfd	sp!, {r4, lr}
     272:		movs	r2, r2, lsl #31
     28		ldmiacs	r1!, {r3, ip}
     29		strcs	r3, [r0, #0]
     30		ldrne	r3, [r1, #0]
     31		strcs	ip, [r0, #0]
     32		strne	r3, [r0, #0]
     33		ret	lr
     34
     353:		bic	r1, r1, #3
     36		ldr	r3, [r1], #4
     37		cmp	ip, #2
     38		blt	5f
     39		bgt	6f
     40
     414:		mov	ip, r3, lspull #16
     42		ldr	r3, [r1], #4
     43		subs	r2, r2, #1
     44		orr	ip, ip, r3, lspush #16
     45		str	ip, [r0]
     46		bne	4b
     47		ret	lr
     48
     495:		mov	ip, r3, lspull #8
     50		ldr	r3, [r1], #4
     51		subs	r2, r2, #1
     52		orr	ip, ip, r3, lspush #24
     53		str	ip, [r0]
     54		bne	5b
     55		ret	lr
     56
     576:		mov	ip, r3, lspull #24
     58		ldr	r3, [r1], #4
     59		subs	r2, r2, #1
     60		orr	ip, ip, r3, lspush #8
     61		str	ip, [r0]
     62		bne	6b
     63		ret	lr
     64ENDPROC(__raw_writesl)