cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pcie.c (8087B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * PCI-E support for CNS3xxx
      4 *
      5 * Copyright 2008 Cavium Networks
      6 *		  Richard Liu <richard.liu@caviumnetworks.com>
      7 * Copyright 2010 MontaVista Software, LLC.
      8 *		  Anton Vorontsov <avorontsov@mvista.com>
      9 */
     10
     11#include <linux/init.h>
     12#include <linux/kernel.h>
     13#include <linux/bug.h>
     14#include <linux/pci.h>
     15#include <linux/io.h>
     16#include <linux/ioport.h>
     17#include <linux/interrupt.h>
     18#include <linux/ptrace.h>
     19#include <asm/mach/map.h>
     20#include "cns3xxx.h"
     21#include "core.h"
     22
     23struct cns3xxx_pcie {
     24	void __iomem *host_regs; /* PCI config registers for host bridge */
     25	void __iomem *cfg0_regs; /* PCI Type 0 config registers */
     26	void __iomem *cfg1_regs; /* PCI Type 1 config registers */
     27	unsigned int irqs[2];
     28	struct resource res_io;
     29	struct resource res_mem;
     30	int port;
     31	bool linked;
     32};
     33
     34static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
     35{
     36	struct pci_sys_data *root = sysdata;
     37
     38	return root->private_data;
     39}
     40
     41static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
     42{
     43	return sysdata_to_cnspci(dev->sysdata);
     44}
     45
     46static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
     47{
     48	return sysdata_to_cnspci(bus->sysdata);
     49}
     50
     51static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
     52					 unsigned int devfn, int where)
     53{
     54	struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
     55	int busno = bus->number;
     56	int slot = PCI_SLOT(devfn);
     57	void __iomem *base;
     58
     59	/* If there is no link, just show the CNS PCI bridge. */
     60	if (!cnspci->linked && busno > 0)
     61		return NULL;
     62
     63	/*
     64	 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
     65	 * we still want to access it.
     66	 * We place the host bridge on bus 0, and the directly connected
     67	 * device on bus 1, slot 0.
     68	 */
     69	if (busno == 0) { /* internal PCIe bus, host bridge device */
     70		if (devfn == 0) /* device# and function# are ignored by hw */
     71			base = cnspci->host_regs;
     72		else
     73			return NULL; /* no such device */
     74
     75	} else if (busno == 1) { /* directly connected PCIe device */
     76		if (slot == 0) /* device# is ignored by hw */
     77			base = cnspci->cfg0_regs;
     78		else
     79			return NULL; /* no such device */
     80	} else /* remote PCI bus */
     81		base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
     82
     83	return base + where + (devfn << 12);
     84}
     85
     86static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
     87				   int where, int size, u32 *val)
     88{
     89	int ret;
     90	u32 mask = (0x1ull << (size * 8)) - 1;
     91	int shift = (where % 4) * 8;
     92
     93	ret = pci_generic_config_read(bus, devfn, where, size, val);
     94
     95	if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
     96	    (where & 0xffc) == PCI_CLASS_REVISION)
     97		/*
     98		 * RC's class is 0xb, but Linux PCI driver needs 0x604
     99		 * for a PCIe bridge. So we must fixup the class code
    100		 * to 0x604 here.
    101		 */
    102		*val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;
    103
    104	return ret;
    105}
    106
    107static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
    108{
    109	struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
    110	struct resource *res_io = &cnspci->res_io;
    111	struct resource *res_mem = &cnspci->res_mem;
    112
    113	BUG_ON(request_resource(&iomem_resource, res_io) ||
    114	       request_resource(&iomem_resource, res_mem));
    115
    116	pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
    117	pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
    118
    119	return 1;
    120}
    121
    122static struct pci_ops cns3xxx_pcie_ops = {
    123	.map_bus = cns3xxx_pci_map_bus,
    124	.read = cns3xxx_pci_read_config,
    125	.write = pci_generic_config_write,
    126};
    127
    128static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
    129{
    130	struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
    131	int irq = cnspci->irqs[!!dev->bus->number];
    132
    133	pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
    134		pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
    135		PCI_FUNC(dev->devfn), slot, pin, irq);
    136
    137	return irq;
    138}
    139
    140static struct cns3xxx_pcie cns3xxx_pcie[] = {
    141	[0] = {
    142		.host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
    143		.cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
    144		.cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
    145		.res_io = {
    146			.name = "PCIe0 I/O space",
    147			.start = CNS3XXX_PCIE0_IO_BASE,
    148			.end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
    149			.flags = IORESOURCE_IO,
    150		},
    151		.res_mem = {
    152			.name = "PCIe0 non-prefetchable",
    153			.start = CNS3XXX_PCIE0_MEM_BASE,
    154			.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
    155			.flags = IORESOURCE_MEM,
    156		},
    157		.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
    158		.port = 0,
    159	},
    160	[1] = {
    161		.host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
    162		.cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
    163		.cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
    164		.res_io = {
    165			.name = "PCIe1 I/O space",
    166			.start = CNS3XXX_PCIE1_IO_BASE,
    167			.end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
    168			.flags = IORESOURCE_IO,
    169		},
    170		.res_mem = {
    171			.name = "PCIe1 non-prefetchable",
    172			.start = CNS3XXX_PCIE1_MEM_BASE,
    173			.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
    174			.flags = IORESOURCE_MEM,
    175		},
    176		.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
    177		.port = 1,
    178	},
    179};
    180
    181static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
    182{
    183	int port = cnspci->port;
    184	u32 reg;
    185	unsigned long time;
    186
    187	reg = __raw_readl(MISC_PCIE_CTRL(port));
    188	/*
    189	 * Enable Application Request to 1, it will exit L1 automatically,
    190	 * but when chip back, it will use another clock, still can use 0x1.
    191	 */
    192	reg |= 0x3;
    193	__raw_writel(reg, MISC_PCIE_CTRL(port));
    194
    195	pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
    196	pr_info("PCIe: Port[%d] Check data link layer...", port);
    197
    198	time = jiffies;
    199	while (1) {
    200		reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
    201		if (reg & 0x1) {
    202			pr_info("Link up.\n");
    203			cnspci->linked = 1;
    204			break;
    205		} else if (time_after(jiffies, time + 50)) {
    206			pr_info("Device not found.\n");
    207			break;
    208		}
    209	}
    210}
    211
    212static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
    213					 int where, int size, u32 val)
    214{
    215	void __iomem *base = cnspci->host_regs + (where & 0xffc);
    216	u32 v;
    217	u32 mask = (0x1ull << (size * 8)) - 1;
    218	int shift = (where % 4) * 8;
    219
    220	v = readl_relaxed(base);
    221
    222	v &= ~(mask << shift);
    223	v |= (val & mask) << shift;
    224
    225	writel_relaxed(v, base);
    226	readl_relaxed(base);
    227}
    228
    229static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
    230{
    231	u16 mem_base  = cnspci->res_mem.start >> 16;
    232	u16 mem_limit = cnspci->res_mem.end   >> 16;
    233	u16 io_base   = cnspci->res_io.start  >> 16;
    234	u16 io_limit  = cnspci->res_io.end    >> 16;
    235
    236	cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
    237	cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
    238	cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
    239	cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
    240	cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
    241	cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
    242	cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);
    243
    244	if (!cnspci->linked)
    245		return;
    246
    247	/* Set Device Max_Read_Request_Size to 128 byte */
    248	pcie_bus_config = PCIE_BUS_PEER2PEER;
    249
    250	/* Disable PCIe0 Interrupt Mask INTA to INTD */
    251	__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));
    252}
    253
    254static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
    255				      struct pt_regs *regs)
    256{
    257	if (fsr & (1 << 10))
    258		regs->ARM_pc += 4;
    259	return 0;
    260}
    261
    262void __init cns3xxx_pcie_init_late(void)
    263{
    264	int i;
    265	void *private_data;
    266	struct hw_pci hw_pci = {
    267	       .nr_controllers = 1,
    268	       .ops = &cns3xxx_pcie_ops,
    269	       .setup = cns3xxx_pci_setup,
    270	       .map_irq = cns3xxx_pcie_map_irq,
    271	       .private_data = &private_data,
    272	};
    273
    274	pcibios_min_io = 0;
    275	pcibios_min_mem = 0;
    276
    277	hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
    278			"imprecise external abort");
    279
    280	for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
    281		cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
    282		cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
    283		cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
    284		cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
    285		private_data = &cns3xxx_pcie[i];
    286		pci_common_init(&hw_pci);
    287	}
    288
    289	pci_assign_unassigned_resources();
    290}