cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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headsmp.S (847B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 *  Cloned from linux/arch/arm/mach-realview/headsmp.S
      4 *
      5 *  Copyright (c) 2003 ARM Limited
      6 *  All Rights Reserved
      7 */
      8#include <linux/linkage.h>
      9#include <linux/init.h>
     10
     11#include <asm/assembler.h>
     12
     13/*
     14 * exynos4 specific entry point for secondary CPUs.  This provides
     15 * a "holding pen" into which all secondary cores are held until we're
     16 * ready for them to initialise.
     17 */
     18ENTRY(exynos4_secondary_startup)
     19ARM_BE8(setend	be)
     20	mrc	p15, 0, r0, c0, c0, 5
     21	and	r0, r0, #15
     22	adr	r4, 1f
     23	ldmia	r4, {r5, r6}
     24	sub	r4, r4, r5
     25	add	r6, r6, r4
     26pen:	ldr	r7, [r6]
     27	cmp	r7, r0
     28	bne	pen
     29
     30	/*
     31	 * we've been released from the holding pen: secondary_stack
     32	 * should now contain the SVC stack for this core
     33	 */
     34	b	secondary_startup
     35ENDPROC(exynos4_secondary_startup)
     36
     37	.align 2
     381:	.long	.
     39	.long	exynos_pen_release