cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mach-imx51.c (2316B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
      4 * Copyright 2011 Linaro Ltd.
      5 */
      6
      7#include <linux/io.h>
      8#include <linux/irq.h>
      9#include <linux/of_address.h>
     10#include <linux/of_irq.h>
     11#include <linux/of_platform.h>
     12#include <asm/mach/arch.h>
     13#include <asm/mach/time.h>
     14
     15#include "common.h"
     16#include "hardware.h"
     17
     18static void __init imx51_init_early(void)
     19{
     20	mxc_set_cpu_type(MXC_CPU_MX51);
     21}
     22
     23/*
     24 * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
     25 * the Freescale marketing division. However this did not remove the
     26 * hardware from the chip which still needs to be configured for proper
     27 * IPU support.
     28 */
     29#define MX51_MIPI_HSC_BASE 0x83fdc000
     30static void __init imx51_ipu_mipi_setup(void)
     31{
     32	void __iomem *hsc_addr;
     33
     34	hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
     35	WARN_ON(!hsc_addr);
     36
     37	/* setup MIPI module to legacy mode */
     38	imx_writel(0xf00, hsc_addr);
     39
     40	/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
     41	imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800);
     42
     43	iounmap(hsc_addr);
     44}
     45
     46static void __init imx51_m4if_setup(void)
     47{
     48	void __iomem *m4if_base;
     49	struct device_node *np;
     50
     51	np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if");
     52	if (!np)
     53		return;
     54
     55	m4if_base = of_iomap(np, 0);
     56	of_node_put(np);
     57	if (!m4if_base) {
     58		pr_err("Unable to map M4IF registers\n");
     59		return;
     60	}
     61
     62	/*
     63	 * Configure VPU and IPU with higher priorities
     64	 * in order to avoid artifacts during video playback
     65	 */
     66	writel_relaxed(0x00000203, m4if_base + 0x40);
     67	writel_relaxed(0x00000000, m4if_base + 0x44);
     68	writel_relaxed(0x00120125, m4if_base + 0x9c);
     69	writel_relaxed(0x001901A3, m4if_base + 0x48);
     70	iounmap(m4if_base);
     71}
     72
     73static void __init imx51_dt_init(void)
     74{
     75	imx51_ipu_mipi_setup();
     76	imx_src_init();
     77	imx51_m4if_setup();
     78	imx5_pmu_init();
     79	imx_aips_allow_unprivileged_access("fsl,imx51-aipstz");
     80}
     81
     82static void __init imx51_init_late(void)
     83{
     84	mx51_neon_fixup();
     85	imx51_pm_init();
     86}
     87
     88static const char * const imx51_dt_board_compat[] __initconst = {
     89	"fsl,imx51",
     90	NULL
     91};
     92
     93DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
     94	.init_early	= imx51_init_early,
     95	.init_machine	= imx51_dt_init,
     96	.init_late	= imx51_init_late,
     97	.dt_compat	= imx51_dt_board_compat,
     98MACHINE_END