cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pm.c (4570B)

      1/*
      2 * arch/arm/mach-lpc32xx/pm.c
      3 *
      4 * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
      5 * Modified by Kevin Wells <kevin.wells@nxp.com>
      6 *
      7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
      8 * the terms of the GNU General Public License version 2. This program
      9 * is licensed "as is" without any warranty of any kind, whether express
     10 * or implied.
     11 */
     12
     13/*
     14 * LPC32XX CPU and system power management
     15 *
     16 * The LPC32XX has three CPU modes for controlling system power: run,
     17 * direct-run, and halt modes. When switching between halt and run modes,
     18 * the CPU transistions through direct-run mode. For Linux, direct-run
     19 * mode is not used in normal operation. Halt mode is used when the
     20 * system is fully suspended.
     21 *
     22 * Run mode:
     23 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
     24 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
     25 * the HCLK_PLL rate. Linux runs in this mode.
     26 *
     27 * Direct-run mode:
     28 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
     29 * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
     30 * source or the frequency of the main oscillator. In this mode, the
     31 * HCLK_PLL can be safely enabled, changed, or disabled.
     32 *
     33 * Halt mode:
     34 * SYSCLK is gated off and the CPU and system clocks are halted.
     35 * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
     36 * key scanner, etc.) still operate if enabled. In this state, an enabled
     37 * system event (ie, GPIO state change, RTC match, key press, etc.) will
     38 * wake the system up back into direct-run mode.
     39 *
     40 * DRAM refresh
     41 * DRAM clocking and refresh are slightly different for systems with DDR
     42 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
     43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
     44 * a transition to direct-run mode will stop all DDR accesses (no clocks).
     45 * Because of this, the code to switch power modes and the code to enter
     46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
     47 * section of IRAM is used instead for this.
     48 *
     49 * Suspend is handled with the following logic:
     50 *  Backup a small area of IRAM used for the suspend code
     51 *  Copy suspend code to IRAM
     52 *  Transfer control to code in IRAM
     53 *  Places DRAMs in self-refresh mode
     54 *  Enter direct-run mode
     55 *  Save state of HCLK_PLL PLL
     56 *  Disable HCLK_PLL PLL
     57 *  Enter halt mode - CPU and buses will stop
     58 *  System enters direct-run mode when an enabled event occurs
     59 *  HCLK PLL state is restored
     60 *  Run mode is entered
     61 *  DRAMS are placed back into normal mode
     62 *  Code execution returns from IRAM
     63 *  IRAM code are used for suspend is restored
     64 *  Suspend mode is exited
     65 */
     66
     67#include <linux/suspend.h>
     68#include <linux/io.h>
     69#include <linux/slab.h>
     70
     71#include <asm/cacheflush.h>
     72
     73#include "lpc32xx.h"
     74#include "common.h"
     75
     76#define TEMP_IRAM_AREA  IO_ADDRESS(LPC32XX_IRAM_BASE)
     77
     78/*
     79 * Both STANDBY and MEM suspend states are handled the same with no
     80 * loss of CPU or memory state
     81 */
     82static int lpc32xx_pm_enter(suspend_state_t state)
     83{
     84	int (*lpc32xx_suspend_ptr) (void);
     85	void *iram_swap_area;
     86
     87	/* Allocate some space for temporary IRAM storage */
     88	iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
     89				 lpc32xx_sys_suspend_sz, GFP_KERNEL);
     90	if (!iram_swap_area)
     91		return -ENOMEM;
     92
     93	/*
     94	 * Copy code to suspend system into IRAM. The suspend code
     95	 * needs to run from IRAM as DRAM may no longer be available
     96	 * when the PLL is stopped.
     97	 */
     98	memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
     99		lpc32xx_sys_suspend_sz);
    100	flush_icache_range((unsigned long)TEMP_IRAM_AREA,
    101		(unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
    102
    103	/* Transfer to suspend code in IRAM */
    104	lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
    105	flush_cache_all();
    106	(void) lpc32xx_suspend_ptr();
    107
    108	/* Restore original IRAM contents */
    109	memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
    110		lpc32xx_sys_suspend_sz);
    111
    112	kfree(iram_swap_area);
    113
    114	return 0;
    115}
    116
    117static const struct platform_suspend_ops lpc32xx_pm_ops = {
    118	.valid	= suspend_valid_only_mem,
    119	.enter	= lpc32xx_pm_enter,
    120};
    121
    122#define EMC_DYN_MEM_CTRL_OFS 0x20
    123#define EMC_SRMMC           (1 << 3)
    124#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
    125static int __init lpc32xx_pm_init(void)
    126{
    127	/*
    128	 * Setup SDRAM self-refresh clock to automatically disable o
    129	 * start of self-refresh. This only needs to be done once.
    130	 */
    131	__raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
    132
    133	suspend_set_ops(&lpc32xx_pm_ops);
    134
    135	return 0;
    136}
    137arch_initcall(lpc32xx_pm_init);