cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bridge-regs.h (1003B)


      1/*
      2 * This file is licensed under the terms of the GNU General Public
      3 * License version 2.  This program is licensed "as is" without any
      4 * warranty of any kind, whether express or implied.
      5 */
      6
      7#ifndef __ASM_ARCH_BRIDGE_REGS_H
      8#define __ASM_ARCH_BRIDGE_REGS_H
      9
     10#include "mv78xx0.h"
     11
     12#define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
     13#define L2_WRITETHROUGH		0x00020000
     14
     15#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
     16#define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)
     17#define SOFT_RESET_OUT_EN	0x00000004
     18
     19#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
     20#define SOFT_RESET		0x00000001
     21
     22#define BRIDGE_INT_TIMER1_CLR	(~0x0004)
     23
     24#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
     25#define IRQ_CAUSE_ERR_OFF	0x0000
     26#define IRQ_CAUSE_LOW_OFF	0x0004
     27#define IRQ_CAUSE_HIGH_OFF	0x0008
     28#define IRQ_MASK_ERR_OFF	0x000c
     29#define IRQ_MASK_LOW_OFF	0x0010
     30#define IRQ_MASK_HIGH_OFF	0x0014
     31
     32#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
     33#define TIMER_PHYS_BASE		(BRIDGE_PHYS_BASE + 0x0300)
     34
     35#endif