cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq.c (1944B)

      1/*
      2 * arch/arm/mach-mv78xx0/irq.c
      3 *
      4 * MV78xx0 IRQ handling.
      5 *
      6 * This file is licensed under the terms of the GNU General Public
      7 * License version 2.  This program is licensed "as is" without any
      8 * warranty of any kind, whether express or implied.
      9 */
     10#include <linux/gpio.h>
     11#include <linux/kernel.h>
     12#include <linux/irq.h>
     13#include <linux/io.h>
     14#include <asm/exception.h>
     15#include <plat/orion-gpio.h>
     16#include <plat/irq.h>
     17#include "bridge-regs.h"
     18#include "common.h"
     19
     20static int __initdata gpio0_irqs[4] = {
     21	IRQ_MV78XX0_GPIO_0_7,
     22	IRQ_MV78XX0_GPIO_8_15,
     23	IRQ_MV78XX0_GPIO_16_23,
     24	IRQ_MV78XX0_GPIO_24_31,
     25};
     26
     27static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
     28
     29static asmlinkage void
     30__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
     31{
     32	u32 stat;
     33
     34	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
     35	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
     36	if (stat) {
     37		unsigned int hwirq = __fls(stat);
     38		handle_IRQ(hwirq, regs);
     39		return;
     40	}
     41	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
     42	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
     43	if (stat) {
     44		unsigned int hwirq = 32 + __fls(stat);
     45		handle_IRQ(hwirq, regs);
     46		return;
     47	}
     48	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
     49	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
     50	if (stat) {
     51		unsigned int hwirq = 64 + __fls(stat);
     52		handle_IRQ(hwirq, regs);
     53		return;
     54	}
     55}
     56
     57void __init mv78xx0_init_irq(void)
     58{
     59	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
     60	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
     61	orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
     62
     63	set_handle_irq(mv78xx0_legacy_handle_irq);
     64
     65	/*
     66	 * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
     67	 * registers for core #1 are at an offset of 0x18 from those of
     68	 * core #0.)
     69	 */
     70	orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0,
     71			IRQ_MV78XX0_GPIO_START, gpio0_irqs);
     72}