cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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headsmp.S (1147B)

      1/*
      2 * SMP support: Entry point for secondary CPUs
      3 *
      4 * Copyright (C) 2012 Marvell
      5 *
      6 * Yehuda Yitschak <yehuday@marvell.com>
      7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
      8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      9 *
     10 * This file is licensed under the terms of the GNU General Public
     11 * License version 2.  This program is licensed "as is" without any
     12 * warranty of any kind, whether express or implied.
     13 *
     14 * This file implements the assembly entry point for secondary CPUs in
     15 * an SMP kernel. The only thing we need to do is to add the CPU to
     16 * the coherency fabric by writing to 2 registers. Currently the base
     17 * register addresses are hard coded due to the early initialisation
     18 * problems.
     19 */
     20
     21#include <linux/linkage.h>
     22#include <linux/init.h>
     23
     24#include <asm/assembler.h>
     25
     26/*
     27 * Armada XP specific entry point for secondary CPUs.
     28 * We add the CPU to the coherency fabric and then jump to secondary
     29 * startup
     30 */
     31ENTRY(armada_xp_secondary_startup)
     32 ARM_BE8(setend	be )			@ go BE8 if entered LE
     33
     34	bl	ll_add_cpu_to_smp_group
     35
     36	bl	ll_enable_coherency
     37
     38	b	secondary_startup
     39
     40ENDPROC(armada_xp_secondary_startup)