cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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board-h3.c (10563B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * linux/arch/arm/mach-omap1/board-h3.c
      4 *
      5 * This file contains OMAP1710 H3 specific code.
      6 *
      7 * Copyright (C) 2004 Texas Instruments, Inc.
      8 * Copyright (C) 2002 MontaVista Software, Inc.
      9 * Copyright (C) 2001 RidgeRun, Inc.
     10 * Author: RidgeRun, Inc.
     11 *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
     12 */
     13#include <linux/gpio.h>
     14#include <linux/types.h>
     15#include <linux/init.h>
     16#include <linux/major.h>
     17#include <linux/kernel.h>
     18#include <linux/platform_device.h>
     19#include <linux/errno.h>
     20#include <linux/workqueue.h>
     21#include <linux/i2c.h>
     22#include <linux/mtd/mtd.h>
     23#include <linux/mtd/platnand.h>
     24#include <linux/mtd/partitions.h>
     25#include <linux/mtd/physmap.h>
     26#include <linux/input.h>
     27#include <linux/spi/spi.h>
     28#include <linux/mfd/tps65010.h>
     29#include <linux/smc91x.h>
     30#include <linux/omapfb.h>
     31#include <linux/platform_data/gpio-omap.h>
     32#include <linux/platform_data/keypad-omap.h>
     33#include <linux/omap-dma.h>
     34#include <linux/leds.h>
     35
     36#include <asm/setup.h>
     37#include <asm/page.h>
     38#include <asm/mach-types.h>
     39#include <asm/mach/arch.h>
     40#include <asm/mach/map.h>
     41
     42#include "tc.h"
     43#include "mux.h"
     44#include "flash.h"
     45#include "hardware.h"
     46#include "irqs.h"
     47#include "usb.h"
     48#include "common.h"
     49#include "board-h3.h"
     50
     51/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
     52#define OMAP1710_ETHR_START		0x04000300
     53
     54#define H3_TS_GPIO	48
     55
     56static const unsigned int h3_keymap[] = {
     57	KEY(0, 0, KEY_LEFT),
     58	KEY(1, 0, KEY_RIGHT),
     59	KEY(2, 0, KEY_3),
     60	KEY(3, 0, KEY_F10),
     61	KEY(4, 0, KEY_F5),
     62	KEY(5, 0, KEY_9),
     63	KEY(0, 1, KEY_DOWN),
     64	KEY(1, 1, KEY_UP),
     65	KEY(2, 1, KEY_2),
     66	KEY(3, 1, KEY_F9),
     67	KEY(4, 1, KEY_F7),
     68	KEY(5, 1, KEY_0),
     69	KEY(0, 2, KEY_ENTER),
     70	KEY(1, 2, KEY_6),
     71	KEY(2, 2, KEY_1),
     72	KEY(3, 2, KEY_F2),
     73	KEY(4, 2, KEY_F6),
     74	KEY(5, 2, KEY_HOME),
     75	KEY(0, 3, KEY_8),
     76	KEY(1, 3, KEY_5),
     77	KEY(2, 3, KEY_F12),
     78	KEY(3, 3, KEY_F3),
     79	KEY(4, 3, KEY_F8),
     80	KEY(5, 3, KEY_END),
     81	KEY(0, 4, KEY_7),
     82	KEY(1, 4, KEY_4),
     83	KEY(2, 4, KEY_F11),
     84	KEY(3, 4, KEY_F1),
     85	KEY(4, 4, KEY_F4),
     86	KEY(5, 4, KEY_ESC),
     87	KEY(0, 5, KEY_F13),
     88	KEY(1, 5, KEY_F14),
     89	KEY(2, 5, KEY_F15),
     90	KEY(3, 5, KEY_F16),
     91	KEY(4, 5, KEY_SLEEP),
     92};
     93
     94
     95static struct mtd_partition nor_partitions[] = {
     96	/* bootloader (U-Boot, etc) in first sector */
     97	{
     98	      .name		= "bootloader",
     99	      .offset		= 0,
    100	      .size		= SZ_128K,
    101	      .mask_flags	= MTD_WRITEABLE, /* force read-only */
    102	},
    103	/* bootloader params in the next sector */
    104	{
    105	      .name		= "params",
    106	      .offset		= MTDPART_OFS_APPEND,
    107	      .size		= SZ_128K,
    108	      .mask_flags	= 0,
    109	},
    110	/* kernel */
    111	{
    112	      .name		= "kernel",
    113	      .offset		= MTDPART_OFS_APPEND,
    114	      .size		= SZ_2M,
    115	      .mask_flags	= 0
    116	},
    117	/* file system */
    118	{
    119	      .name		= "filesystem",
    120	      .offset		= MTDPART_OFS_APPEND,
    121	      .size		= MTDPART_SIZ_FULL,
    122	      .mask_flags	= 0
    123	}
    124};
    125
    126static struct physmap_flash_data nor_data = {
    127	.width		= 2,
    128	.set_vpp	= omap1_set_vpp,
    129	.parts		= nor_partitions,
    130	.nr_parts	= ARRAY_SIZE(nor_partitions),
    131};
    132
    133static struct resource nor_resource = {
    134	/* This is on CS3, wherever it's mapped */
    135	.flags		= IORESOURCE_MEM,
    136};
    137
    138static struct platform_device nor_device = {
    139	.name		= "physmap-flash",
    140	.id		= 0,
    141	.dev		= {
    142		.platform_data	= &nor_data,
    143	},
    144	.num_resources	= 1,
    145	.resource	= &nor_resource,
    146};
    147
    148static struct mtd_partition nand_partitions[] = {
    149#if 0
    150	/* REVISIT: enable these partitions if you make NAND BOOT work */
    151	{
    152		.name		= "xloader",
    153		.offset		= 0,
    154		.size		= 64 * 1024,
    155		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
    156	},
    157	{
    158		.name		= "bootloader",
    159		.offset		= MTDPART_OFS_APPEND,
    160		.size		= 256 * 1024,
    161		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
    162	},
    163	{
    164		.name		= "params",
    165		.offset		= MTDPART_OFS_APPEND,
    166		.size		= 192 * 1024,
    167	},
    168	{
    169		.name		= "kernel",
    170		.offset		= MTDPART_OFS_APPEND,
    171		.size		= 2 * SZ_1M,
    172	},
    173#endif
    174	{
    175		.name		= "filesystem",
    176		.size		= MTDPART_SIZ_FULL,
    177		.offset		= MTDPART_OFS_APPEND,
    178	},
    179};
    180
    181#define H3_NAND_RB_GPIO_PIN	10
    182
    183static int nand_dev_ready(struct nand_chip *chip)
    184{
    185	return gpio_get_value(H3_NAND_RB_GPIO_PIN);
    186}
    187
    188static struct platform_nand_data nand_platdata = {
    189	.chip	= {
    190		.nr_chips		= 1,
    191		.chip_offset		= 0,
    192		.nr_partitions		= ARRAY_SIZE(nand_partitions),
    193		.partitions		= nand_partitions,
    194		.options		= NAND_SAMSUNG_LP_OPTIONS,
    195	},
    196	.ctrl	= {
    197		.cmd_ctrl	= omap1_nand_cmd_ctl,
    198		.dev_ready	= nand_dev_ready,
    199
    200	},
    201};
    202
    203static struct resource nand_resource = {
    204	.flags		= IORESOURCE_MEM,
    205};
    206
    207static struct platform_device nand_device = {
    208	.name		= "gen_nand",
    209	.id		= 0,
    210	.dev		= {
    211		.platform_data	= &nand_platdata,
    212	},
    213	.num_resources	= 1,
    214	.resource	= &nand_resource,
    215};
    216
    217static struct smc91x_platdata smc91x_info = {
    218	.flags	= SMC91X_USE_16BIT | SMC91X_NOWAIT,
    219	.leda	= RPC_LED_100_10,
    220	.ledb	= RPC_LED_TX_RX,
    221};
    222
    223static struct resource smc91x_resources[] = {
    224	[0] = {
    225		.start	= OMAP1710_ETHR_START,		/* Physical */
    226		.end	= OMAP1710_ETHR_START + 0xf,
    227		.flags	= IORESOURCE_MEM,
    228	},
    229	[1] = {
    230		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
    231	},
    232};
    233
    234static struct platform_device smc91x_device = {
    235	.name		= "smc91x",
    236	.id		= 0,
    237	.dev	= {
    238		.platform_data	= &smc91x_info,
    239	},
    240	.num_resources	= ARRAY_SIZE(smc91x_resources),
    241	.resource	= smc91x_resources,
    242};
    243
    244static void __init h3_init_smc91x(void)
    245{
    246	omap_cfg_reg(W15_1710_GPIO40);
    247	if (gpio_request(40, "SMC91x irq") < 0) {
    248		printk("Error requesting gpio 40 for smc91x irq\n");
    249		return;
    250	}
    251}
    252
    253#define GPTIMER_BASE		0xFFFB1400
    254#define GPTIMER_REGS(x)	(0xFFFB1400 + (x * 0x800))
    255#define GPTIMER_REGS_SIZE	0x46
    256
    257static struct resource intlat_resources[] = {
    258	[0] = {
    259		.start  = GPTIMER_REGS(0),	      /* Physical */
    260		.end    = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
    261		.flags  = IORESOURCE_MEM,
    262	},
    263	[1] = {
    264		.start  = INT_1610_GPTIMER1,
    265		.end    = INT_1610_GPTIMER1,
    266		.flags  = IORESOURCE_IRQ,
    267	},
    268};
    269
    270static struct platform_device intlat_device = {
    271	.name	   = "omap_intlat",
    272	.id	     = 0,
    273	.num_resources  = ARRAY_SIZE(intlat_resources),
    274	.resource       = intlat_resources,
    275};
    276
    277static struct resource h3_kp_resources[] = {
    278	[0] = {
    279		.start	= INT_KEYBOARD,
    280		.end	= INT_KEYBOARD,
    281		.flags	= IORESOURCE_IRQ,
    282	},
    283};
    284
    285static const struct matrix_keymap_data h3_keymap_data = {
    286	.keymap		= h3_keymap,
    287	.keymap_size	= ARRAY_SIZE(h3_keymap),
    288};
    289
    290static struct omap_kp_platform_data h3_kp_data = {
    291	.rows		= 8,
    292	.cols		= 8,
    293	.keymap_data	= &h3_keymap_data,
    294	.rep		= true,
    295	.delay		= 9,
    296	.dbounce	= true,
    297};
    298
    299static struct platform_device h3_kp_device = {
    300	.name		= "omap-keypad",
    301	.id		= -1,
    302	.dev		= {
    303		.platform_data = &h3_kp_data,
    304	},
    305	.num_resources	= ARRAY_SIZE(h3_kp_resources),
    306	.resource	= h3_kp_resources,
    307};
    308
    309static struct platform_device h3_lcd_device = {
    310	.name		= "lcd_h3",
    311	.id		= -1,
    312};
    313
    314static struct spi_board_info h3_spi_board_info[] __initdata = {
    315	[0] = {
    316		.modalias	= "tsc2101",
    317		.bus_num	= 2,
    318		.chip_select	= 0,
    319		.max_speed_hz	= 16000000,
    320		/* .platform_data	= &tsc_platform_data, */
    321	},
    322};
    323
    324static const struct gpio_led h3_gpio_led_pins[] = {
    325	{
    326		.name		= "h3:red",
    327		.default_trigger = "heartbeat",
    328		.gpio		= 3,
    329	},
    330	{
    331		.name		= "h3:green",
    332		.default_trigger = "cpu0",
    333		.gpio		= OMAP_MPUIO(4),
    334	},
    335};
    336
    337static struct gpio_led_platform_data h3_gpio_led_data = {
    338	.leds		= h3_gpio_led_pins,
    339	.num_leds	= ARRAY_SIZE(h3_gpio_led_pins),
    340};
    341
    342static struct platform_device h3_gpio_leds = {
    343	.name	= "leds-gpio",
    344	.id	= -1,
    345	.dev	= {
    346		.platform_data = &h3_gpio_led_data,
    347	},
    348};
    349
    350static struct platform_device *devices[] __initdata = {
    351	&nor_device,
    352	&nand_device,
    353        &smc91x_device,
    354	&intlat_device,
    355	&h3_kp_device,
    356	&h3_lcd_device,
    357	&h3_gpio_leds,
    358};
    359
    360static struct omap_usb_config h3_usb_config __initdata = {
    361	/* usb1 has a Mini-AB port and external isp1301 transceiver */
    362	.otg	    = 2,
    363
    364#if IS_ENABLED(CONFIG_USB_OMAP)
    365	.hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
    366#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
    367	/* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
    368	.hmc_mode       = 20,   /* 1:dev|otg(off) 1:host 2:disabled */
    369#endif
    370
    371	.pins[1]	= 3,
    372};
    373
    374static const struct omap_lcd_config h3_lcd_config __initconst = {
    375	.ctrl_name	= "internal",
    376};
    377
    378static struct i2c_board_info __initdata h3_i2c_board_info[] = {
    379       {
    380		I2C_BOARD_INFO("tps65013", 0x48),
    381       },
    382	{
    383		I2C_BOARD_INFO("isp1301_omap", 0x2d),
    384	},
    385};
    386
    387static void __init h3_init(void)
    388{
    389	h3_init_smc91x();
    390
    391	/* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
    392	 * to address 0 by a dip switch), NAND on CS2B.  The NAND driver will
    393	 * notice whether a NAND chip is enabled at probe time.
    394	 *
    395	 * H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND
    396	 * (which on H2 may be 16bit) on CS3.  Try detecting that in code here,
    397	 * to avoid probing every possible flash configuration...
    398	 */
    399	nor_resource.end = nor_resource.start = omap_cs3_phys();
    400	nor_resource.end += SZ_32M - 1;
    401
    402	nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS;
    403	nand_resource.end += SZ_4K - 1;
    404	BUG_ON(gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0);
    405	gpio_direction_input(H3_NAND_RB_GPIO_PIN);
    406
    407	/* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
    408	/* GPIO10 pullup/down register, Enable pullup on GPIO10 */
    409	omap_cfg_reg(V2_1710_GPIO10);
    410
    411	/* Mux pins for keypad */
    412	omap_cfg_reg(F18_1610_KBC0);
    413	omap_cfg_reg(D20_1610_KBC1);
    414	omap_cfg_reg(D19_1610_KBC2);
    415	omap_cfg_reg(E18_1610_KBC3);
    416	omap_cfg_reg(C21_1610_KBC4);
    417	omap_cfg_reg(G18_1610_KBR0);
    418	omap_cfg_reg(F19_1610_KBR1);
    419	omap_cfg_reg(H14_1610_KBR2);
    420	omap_cfg_reg(E20_1610_KBR3);
    421	omap_cfg_reg(E19_1610_KBR4);
    422	omap_cfg_reg(N19_1610_KBR5);
    423
    424	/* GPIO based LEDs */
    425	omap_cfg_reg(P18_1610_GPIO3);
    426	omap_cfg_reg(MPUIO4);
    427
    428	smc91x_resources[1].start = gpio_to_irq(40);
    429	smc91x_resources[1].end = gpio_to_irq(40);
    430	platform_add_devices(devices, ARRAY_SIZE(devices));
    431	h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO);
    432	spi_register_board_info(h3_spi_board_info,
    433				ARRAY_SIZE(h3_spi_board_info));
    434	omap_serial_init();
    435	h3_i2c_board_info[1].irq = gpio_to_irq(14);
    436	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
    437			      ARRAY_SIZE(h3_i2c_board_info));
    438	omap1_usb_init(&h3_usb_config);
    439	h3_mmc_init();
    440
    441	omapfb_set_lcd_config(&h3_lcd_config);
    442}
    443
    444MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
    445	/* Maintainer: Texas Instruments, Inc. */
    446	.atag_offset	= 0x100,
    447	.map_io		= omap16xx_map_io,
    448	.init_early     = omap1_init_early,
    449	.init_irq	= omap1_init_irq,
    450	.handle_irq	= omap1_handle_irq,
    451	.init_machine	= h3_init,
    452	.init_late	= omap1_init_late,
    453	.init_time	= omap1_timer_init,
    454	.restart	= omap1_restart,
    455MACHINE_END