hardware.h (6882B)
1/* 2 * Hardware definitions for TI OMAP processors and boards 3 * 4 * NOTE: Please put device driver specific defines into a separate header 5 * file for each driver. 6 * 7 * Copyright (C) 2001 RidgeRun, Inc. 8 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 9 * 10 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> 11 * and Dirk Behme <dirk.behme@de.bosch.com> 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, write to the Free Software Foundation, Inc., 31 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 */ 33 34#ifndef __ASM_ARCH_OMAP_HARDWARE_H 35#define __ASM_ARCH_OMAP_HARDWARE_H 36 37#include <linux/sizes.h> 38#include <linux/soc/ti/omap1-io.h> 39#ifndef __ASSEMBLER__ 40#include <asm/types.h> 41#include <linux/soc/ti/omap1-soc.h> 42 43#include "tc.h" 44 45/* Almost all documentation for chip and board memory maps assumes 46 * BM is clear. Most devel boards have a switch to control booting 47 * from NOR flash (using external chipselect 3) rather than mask ROM, 48 * which uses BM to interchange the physical CS0 and CS3 addresses. 49 */ 50static inline u32 omap_cs0m_phys(void) 51{ 52 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) 53 ? OMAP_CS3_PHYS : 0; 54} 55 56static inline u32 omap_cs3_phys(void) 57{ 58 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) 59 ? 0 : OMAP_CS3_PHYS; 60} 61 62#endif /* ifndef __ASSEMBLER__ */ 63 64#define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */ 65#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) 66 67#include "serial.h" 68 69/* 70 * --------------------------------------------------------------------------- 71 * Common definitions for all OMAP processors 72 * NOTE: Put all processor or board specific parts to the special header 73 * files. 74 * --------------------------------------------------------------------------- 75 */ 76 77/* 78 * ---------------------------------------------------------------------------- 79 * Timers 80 * ---------------------------------------------------------------------------- 81 */ 82#define OMAP_MPU_TIMER1_BASE (0xfffec500) 83#define OMAP_MPU_TIMER2_BASE (0xfffec600) 84#define OMAP_MPU_TIMER3_BASE (0xfffec700) 85#define MPU_TIMER_FREE (1 << 6) 86#define MPU_TIMER_CLOCK_ENABLE (1 << 5) 87#define MPU_TIMER_AR (1 << 1) 88#define MPU_TIMER_ST (1 << 0) 89 90/* 91 * --------------------------------------------------------------------------- 92 * Watchdog timer 93 * --------------------------------------------------------------------------- 94 */ 95 96/* Watchdog timer within the OMAP3.2 gigacell */ 97#define OMAP_MPU_WATCHDOG_BASE (0xfffec800) 98#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) 99#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) 100#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) 101#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) 102 103/* 104 * --------------------------------------------------------------------------- 105 * Interrupts 106 * --------------------------------------------------------------------------- 107 */ 108#ifdef CONFIG_ARCH_OMAP1 109 110/* 111 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c 112 * or something similar.. -- PFM. 113 */ 114 115#define OMAP_IH1_BASE 0xfffecb00 116#define OMAP_IH2_BASE 0xfffe0000 117 118#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) 119#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) 120#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) 121#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) 122#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) 123#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) 124#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) 125 126#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) 127#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) 128#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) 129#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) 130#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) 131#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) 132#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) 133 134#define IRQ_ITR_REG_OFFSET 0x00 135#define IRQ_MIR_REG_OFFSET 0x04 136#define IRQ_SIR_IRQ_REG_OFFSET 0x10 137#define IRQ_SIR_FIQ_REG_OFFSET 0x14 138#define IRQ_CONTROL_REG_OFFSET 0x18 139#define IRQ_ISR_REG_OFFSET 0x9c 140#define IRQ_ILR0_REG_OFFSET 0x1c 141#define IRQ_GMR_REG_OFFSET 0xa0 142 143#endif 144 145/* Timer32K for 1610 and 1710*/ 146#define OMAP_TIMER32K_BASE 0xFFFBC400 147 148/* 149 * --------------------------------------------------------------------------- 150 * TIPB bus interface 151 * --------------------------------------------------------------------------- 152 */ 153#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 154#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) 155#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 156#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) 157 158/* 159 * ---------------------------------------------------------------------------- 160 * MPUI interface 161 * ---------------------------------------------------------------------------- 162 */ 163#define MPUI_BASE (0xfffec900) 164#define MPUI_CTRL (MPUI_BASE + 0x0) 165#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) 166#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) 167#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) 168#define MPUI_STATUS_REG (MPUI_BASE + 0x10) 169#define MPUI_DSP_STATUS (MPUI_BASE + 0x14) 170#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) 171#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) 172 173/* 174 * ---------------------------------------------------------------------------- 175 * LED Pulse Generator 176 * ---------------------------------------------------------------------------- 177 */ 178#define OMAP_LPG1_BASE 0xfffbd000 179#define OMAP_LPG2_BASE 0xfffbd800 180#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) 181#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) 182#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) 183#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) 184 185/* 186 * --------------------------------------------------------------------------- 187 * Processor specific defines 188 * --------------------------------------------------------------------------- 189 */ 190 191#include "omap7xx.h" 192#include "omap1510.h" 193#include "omap16xx.h" 194 195#endif /* __ASM_ARCH_OMAP_HARDWARE_H */