cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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timer.c (4161B)

      1/*
      2 * OMAP1 Dual-Mode Timers - platform device registration
      3 *
      4 * Contains first level initialization routines which internally
      5 * generates timer device information and registers with linux
      6 * device model. It also has a low level function to change the timer
      7 * input clock source.
      8 *
      9 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
     10 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
     11 * Thara Gopinath <thara@ti.com>
     12 *
     13 * This program is free software; you can redistribute it and/or modify
     14 * it under the terms of the GNU General Public License version 2 as
     15 * published by the Free Software Foundation.
     16 *
     17 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
     18 * kind, whether express or implied; without even the implied warranty
     19 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     20 * GNU General Public License for more details.
     21 */
     22
     23#include <linux/clk.h>
     24#include <linux/io.h>
     25#include <linux/err.h>
     26#include <linux/slab.h>
     27#include <linux/platform_device.h>
     28#include <linux/platform_data/dmtimer-omap.h>
     29#include <linux/soc/ti/omap1-io.h>
     30
     31#include <clocksource/timer-ti-dm.h>
     32
     33#include "soc.h"
     34
     35#define OMAP1610_GPTIMER1_BASE		0xfffb1400
     36#define OMAP1610_GPTIMER2_BASE		0xfffb1c00
     37#define OMAP1610_GPTIMER3_BASE		0xfffb2400
     38#define OMAP1610_GPTIMER4_BASE		0xfffb2c00
     39#define OMAP1610_GPTIMER5_BASE		0xfffb3400
     40#define OMAP1610_GPTIMER6_BASE		0xfffb3c00
     41#define OMAP1610_GPTIMER7_BASE		0xfffb7400
     42#define OMAP1610_GPTIMER8_BASE		0xfffbd400
     43
     44#define OMAP1_DM_TIMER_COUNT		8
     45
     46static int omap1_dm_timer_set_src(struct platform_device *pdev,
     47				int source)
     48{
     49	int n = (pdev->id - 1) << 1;
     50	u32 l;
     51
     52	l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
     53	l |= source << n;
     54	omap_writel(l, MOD_CONF_CTRL_1);
     55
     56	return 0;
     57}
     58
     59static int __init omap1_dm_timer_init(void)
     60{
     61	int i;
     62	int ret;
     63	struct dmtimer_platform_data *pdata;
     64	struct platform_device *pdev;
     65
     66	if (!cpu_is_omap16xx())
     67		return 0;
     68
     69	for (i = 1; i <= OMAP1_DM_TIMER_COUNT; i++) {
     70		struct resource res[2];
     71		u32 base, irq;
     72
     73		switch (i) {
     74		case 1:
     75			base = OMAP1610_GPTIMER1_BASE;
     76			irq = INT_1610_GPTIMER1;
     77			break;
     78		case 2:
     79			base = OMAP1610_GPTIMER2_BASE;
     80			irq = INT_1610_GPTIMER2;
     81			break;
     82		case 3:
     83			base = OMAP1610_GPTIMER3_BASE;
     84			irq = INT_1610_GPTIMER3;
     85			break;
     86		case 4:
     87			base = OMAP1610_GPTIMER4_BASE;
     88			irq = INT_1610_GPTIMER4;
     89			break;
     90		case 5:
     91			base = OMAP1610_GPTIMER5_BASE;
     92			irq = INT_1610_GPTIMER5;
     93			break;
     94		case 6:
     95			base = OMAP1610_GPTIMER6_BASE;
     96			irq = INT_1610_GPTIMER6;
     97			break;
     98		case 7:
     99			base = OMAP1610_GPTIMER7_BASE;
    100			irq = INT_1610_GPTIMER7;
    101			break;
    102		case 8:
    103			base = OMAP1610_GPTIMER8_BASE;
    104			irq = INT_1610_GPTIMER8;
    105			break;
    106		default:
    107			/*
    108			 * not supposed to reach here.
    109			 * this is to remove warning.
    110			 */
    111			return -EINVAL;
    112		}
    113
    114		pdev = platform_device_alloc("omap_timer", i);
    115		if (!pdev) {
    116			pr_err("%s: Failed to device alloc for dmtimer%d\n",
    117				__func__, i);
    118			return -ENOMEM;
    119		}
    120
    121		memset(res, 0, 2 * sizeof(struct resource));
    122		res[0].start = base;
    123		res[0].end = base + 0x46;
    124		res[0].flags = IORESOURCE_MEM;
    125		res[1].start = irq;
    126		res[1].end = irq;
    127		res[1].flags = IORESOURCE_IRQ;
    128		ret = platform_device_add_resources(pdev, res,
    129				ARRAY_SIZE(res));
    130		if (ret) {
    131			dev_err(&pdev->dev, "%s: Failed to add resources.\n",
    132				__func__);
    133			goto err_free_pdev;
    134		}
    135
    136		pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
    137		if (!pdata) {
    138			ret = -ENOMEM;
    139			goto err_free_pdata;
    140		}
    141
    142		pdata->set_timer_src = omap1_dm_timer_set_src;
    143		pdata->timer_capability = OMAP_TIMER_ALWON |
    144				OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
    145
    146		ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
    147		if (ret) {
    148			dev_err(&pdev->dev, "%s: Failed to add platform data.\n",
    149				__func__);
    150			goto err_free_pdata;
    151		}
    152
    153		ret = platform_device_add(pdev);
    154		if (ret) {
    155			dev_err(&pdev->dev, "%s: Failed to add platform device.\n",
    156				__func__);
    157			goto err_free_pdata;
    158		}
    159
    160		dev_dbg(&pdev->dev, " Registered.\n");
    161	}
    162
    163	return 0;
    164
    165err_free_pdata:
    166	kfree(pdata);
    167
    168err_free_pdev:
    169	platform_device_unregister(pdev);
    170
    171	return ret;
    172}
    173arch_initcall(omap1_dm_timer_init);