cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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usb.c (16934B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Platform level USB initialization for FS USB OTG controller on omap1
      4 *
      5 * Copyright (C) 2004 Texas Instruments, Inc.
      6 */
      7
      8#include <linux/module.h>
      9#include <linux/kernel.h>
     10#include <linux/init.h>
     11#include <linux/platform_device.h>
     12#include <linux/dma-map-ops.h>
     13#include <linux/io.h>
     14#include <linux/delay.h>
     15#include <linux/soc/ti/omap1-io.h>
     16
     17#include <asm/irq.h>
     18
     19#include "hardware.h"
     20#include "mux.h"
     21#include "usb.h"
     22#include "common.h"
     23
     24/* These routines should handle the standard chip-specific modes
     25 * for usb0/1/2 ports, covering basic mux and transceiver setup.
     26 *
     27 * Some board-*.c files will need to set up additional mux options,
     28 * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
     29 */
     30
     31/* TESTED ON:
     32 *  - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
     33 *  - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
     34 *  - 5912 OSK UDC, with *nonstandard* A-to-A cable
     35 *  - 1510 Innovator UDC with bundled usb0 cable
     36 *  - 1510 Innovator OHCI with bundled usb1/usb2 cable
     37 *  - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
     38 *  - 1710 custom development board using alternate pin group
     39 *  - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
     40 */
     41
     42#define INT_USB_IRQ_GEN		IH2_BASE + 20
     43#define INT_USB_IRQ_NISO	IH2_BASE + 30
     44#define INT_USB_IRQ_ISO		IH2_BASE + 29
     45#define INT_USB_IRQ_HGEN	INT_USB_HHC_1
     46#define INT_USB_IRQ_OTG		IH2_BASE + 8
     47
     48#ifdef	CONFIG_ARCH_OMAP_OTG
     49
     50static void __init
     51omap_otg_init(struct omap_usb_config *config)
     52{
     53	u32		syscon;
     54	int		alt_pingroup = 0;
     55	u16		w;
     56
     57	/* NOTE:  no bus or clock setup (yet?) */
     58
     59	syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
     60	if (!(syscon & OTG_RESET_DONE))
     61		pr_debug("USB resets not complete?\n");
     62
     63	//omap_writew(0, OTG_IRQ_EN);
     64
     65	/* pin muxing and transceiver pinouts */
     66	if (config->pins[0] > 2)	/* alt pingroup 2 */
     67		alt_pingroup = 1;
     68	syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
     69	syscon |= config->usb1_init(config->pins[1]);
     70	syscon |= config->usb2_init(config->pins[2], alt_pingroup);
     71	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
     72	omap_writel(syscon, OTG_SYSCON_1);
     73
     74	syscon = config->hmc_mode;
     75	syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
     76#ifdef	CONFIG_USB_OTG
     77	if (config->otg)
     78		syscon |= OTG_EN;
     79#endif
     80	pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
     81		 omap_readl(USB_TRANSCEIVER_CTRL));
     82	pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
     83	omap_writel(syscon, OTG_SYSCON_2);
     84
     85	printk("USB: hmc %d", config->hmc_mode);
     86	if (!alt_pingroup)
     87		pr_cont(", usb2 alt %d wires", config->pins[2]);
     88	else if (config->pins[0])
     89		pr_cont(", usb0 %d wires%s", config->pins[0],
     90			is_usb0_device(config) ? " (dev)" : "");
     91	if (config->pins[1])
     92		pr_cont(", usb1 %d wires", config->pins[1]);
     93	if (!alt_pingroup && config->pins[2])
     94		pr_cont(", usb2 %d wires", config->pins[2]);
     95	if (config->otg)
     96		pr_cont(", Mini-AB on usb%d", config->otg - 1);
     97	pr_cont("\n");
     98
     99	/* leave USB clocks/controllers off until needed */
    100	w = omap_readw(ULPD_SOFT_REQ);
    101	w &= ~SOFT_USB_CLK_REQ;
    102	omap_writew(w, ULPD_SOFT_REQ);
    103
    104	w = omap_readw(ULPD_CLOCK_CTRL);
    105	w &= ~USB_MCLK_EN;
    106	w |= DIS_USB_PVCI_CLK;
    107	omap_writew(w, ULPD_CLOCK_CTRL);
    108
    109	syscon = omap_readl(OTG_SYSCON_1);
    110	syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
    111
    112#if IS_ENABLED(CONFIG_USB_OMAP)
    113	if (config->otg || config->register_dev) {
    114		struct platform_device *udc_device = config->udc_device;
    115		int status;
    116
    117		syscon &= ~DEV_IDLE_EN;
    118		udc_device->dev.platform_data = config;
    119		status = platform_device_register(udc_device);
    120		if (status)
    121			pr_debug("can't register UDC device, %d\n", status);
    122	}
    123#endif
    124
    125#if	IS_ENABLED(CONFIG_USB_OHCI_HCD)
    126	if (config->otg || config->register_host) {
    127		struct platform_device *ohci_device = config->ohci_device;
    128		int status;
    129
    130		syscon &= ~HST_IDLE_EN;
    131		ohci_device->dev.platform_data = config;
    132		status = platform_device_register(ohci_device);
    133		if (status)
    134			pr_debug("can't register OHCI device, %d\n", status);
    135	}
    136#endif
    137
    138#ifdef	CONFIG_USB_OTG
    139	if (config->otg) {
    140		struct platform_device *otg_device = config->otg_device;
    141		int status;
    142
    143		syscon &= ~OTG_IDLE_EN;
    144		otg_device->dev.platform_data = config;
    145		status = platform_device_register(otg_device);
    146		if (status)
    147			pr_debug("can't register OTG device, %d\n", status);
    148	}
    149#endif
    150	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
    151	omap_writel(syscon, OTG_SYSCON_1);
    152}
    153
    154#else
    155static void omap_otg_init(struct omap_usb_config *config) {}
    156#endif
    157
    158#if IS_ENABLED(CONFIG_USB_OMAP)
    159
    160static struct resource udc_resources[] = {
    161	/* order is significant! */
    162	{		/* registers */
    163		.start		= UDC_BASE,
    164		.end		= UDC_BASE + 0xff,
    165		.flags		= IORESOURCE_MEM,
    166	}, {		/* general IRQ */
    167		.start		= INT_USB_IRQ_GEN,
    168		.flags		= IORESOURCE_IRQ,
    169	}, {		/* PIO IRQ */
    170		.start		= INT_USB_IRQ_NISO,
    171		.flags		= IORESOURCE_IRQ,
    172	}, {		/* SOF IRQ */
    173		.start		= INT_USB_IRQ_ISO,
    174		.flags		= IORESOURCE_IRQ,
    175	},
    176};
    177
    178static u64 udc_dmamask = ~(u32)0;
    179
    180static struct platform_device udc_device = {
    181	.name		= "omap_udc",
    182	.id		= -1,
    183	.dev = {
    184		.dma_mask		= &udc_dmamask,
    185		.coherent_dma_mask	= 0xffffffff,
    186	},
    187	.num_resources	= ARRAY_SIZE(udc_resources),
    188	.resource	= udc_resources,
    189};
    190
    191static inline void udc_device_init(struct omap_usb_config *pdata)
    192{
    193	/* IRQ numbers for omap7xx */
    194	if(cpu_is_omap7xx()) {
    195		udc_resources[1].start = INT_7XX_USB_GENI;
    196		udc_resources[2].start = INT_7XX_USB_NON_ISO;
    197		udc_resources[3].start = INT_7XX_USB_ISO;
    198	}
    199	pdata->udc_device = &udc_device;
    200}
    201
    202#else
    203
    204static inline void udc_device_init(struct omap_usb_config *pdata)
    205{
    206}
    207
    208#endif
    209
    210/* The dmamask must be set for OHCI to work */
    211static u64 ohci_dmamask = ~(u32)0;
    212
    213static struct resource ohci_resources[] = {
    214	{
    215		.start	= OMAP_OHCI_BASE,
    216		.end	= OMAP_OHCI_BASE + 0xff,
    217		.flags	= IORESOURCE_MEM,
    218	},
    219	{
    220		.start	= INT_USB_IRQ_HGEN,
    221		.flags	= IORESOURCE_IRQ,
    222	},
    223};
    224
    225static struct platform_device ohci_device = {
    226	.name			= "ohci",
    227	.id			= -1,
    228	.dev = {
    229		.dma_mask		= &ohci_dmamask,
    230		.coherent_dma_mask	= 0xffffffff,
    231	},
    232	.num_resources	= ARRAY_SIZE(ohci_resources),
    233	.resource		= ohci_resources,
    234};
    235
    236static inline void ohci_device_init(struct omap_usb_config *pdata)
    237{
    238	if (!IS_ENABLED(CONFIG_USB_OHCI_HCD))
    239		return;
    240
    241	if (cpu_is_omap7xx())
    242		ohci_resources[1].start = INT_7XX_USB_HHC_1;
    243	pdata->ohci_device = &ohci_device;
    244	pdata->ocpi_enable = &ocpi_enable;
    245}
    246
    247#if	defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
    248
    249static struct resource otg_resources[] = {
    250	/* order is significant! */
    251	{
    252		.start		= OTG_BASE,
    253		.end		= OTG_BASE + 0xff,
    254		.flags		= IORESOURCE_MEM,
    255	}, {
    256		.start		= INT_USB_IRQ_OTG,
    257		.flags		= IORESOURCE_IRQ,
    258	},
    259};
    260
    261static struct platform_device otg_device = {
    262	.name		= "omap_otg",
    263	.id		= -1,
    264	.num_resources	= ARRAY_SIZE(otg_resources),
    265	.resource	= otg_resources,
    266};
    267
    268static inline void otg_device_init(struct omap_usb_config *pdata)
    269{
    270	if (cpu_is_omap7xx())
    271		otg_resources[1].start = INT_7XX_USB_OTG;
    272	pdata->otg_device = &otg_device;
    273}
    274
    275#else
    276
    277static inline void otg_device_init(struct omap_usb_config *pdata)
    278{
    279}
    280
    281#endif
    282
    283static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
    284{
    285	u32	syscon1 = 0;
    286
    287	if (nwires == 0) {
    288		if (!cpu_is_omap15xx()) {
    289			u32 l;
    290
    291			/* pulldown D+/D- */
    292			l = omap_readl(USB_TRANSCEIVER_CTRL);
    293			l &= ~(3 << 1);
    294			omap_writel(l, USB_TRANSCEIVER_CTRL);
    295		}
    296		return 0;
    297	}
    298
    299	if (is_device) {
    300		if (cpu_is_omap7xx()) {
    301			omap_cfg_reg(AA17_7XX_USB_DM);
    302			omap_cfg_reg(W16_7XX_USB_PU_EN);
    303			omap_cfg_reg(W17_7XX_USB_VBUSI);
    304			omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
    305			omap_cfg_reg(W19_7XX_USB_DCRST);
    306		} else
    307			omap_cfg_reg(W4_USB_PUEN);
    308	}
    309
    310	if (nwires == 2) {
    311		u32 l;
    312
    313		// omap_cfg_reg(P9_USB_DP);
    314		// omap_cfg_reg(R8_USB_DM);
    315
    316		if (cpu_is_omap15xx()) {
    317			/* This works on 1510-Innovator */
    318			return 0;
    319		}
    320
    321		/* NOTES:
    322		 *  - peripheral should configure VBUS detection!
    323		 *  - only peripherals may use the internal D+/D- pulldowns
    324		 *  - OTG support on this port not yet written
    325		 */
    326
    327		/* Don't do this for omap7xx -- it causes USB to not work correctly */
    328		if (!cpu_is_omap7xx()) {
    329			l = omap_readl(USB_TRANSCEIVER_CTRL);
    330			l &= ~(7 << 4);
    331			if (!is_device)
    332				l |= (3 << 1);
    333			omap_writel(l, USB_TRANSCEIVER_CTRL);
    334		}
    335
    336		return 3 << 16;
    337	}
    338
    339	/* alternate pin config, external transceiver */
    340	if (cpu_is_omap15xx()) {
    341		printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
    342		return 0;
    343	}
    344
    345	omap_cfg_reg(V6_USB0_TXD);
    346	omap_cfg_reg(W9_USB0_TXEN);
    347	omap_cfg_reg(W5_USB0_SE0);
    348	if (nwires != 3)
    349		omap_cfg_reg(Y5_USB0_RCV);
    350
    351	/* NOTE:  SPEED and SUSP aren't configured here.  OTG hosts
    352	 * may be able to use I2C requests to set those bits along
    353	 * with VBUS switching and overcurrent detection.
    354	 */
    355
    356	if (nwires != 6) {
    357		u32 l;
    358
    359		l = omap_readl(USB_TRANSCEIVER_CTRL);
    360		l &= ~CONF_USB2_UNI_R;
    361		omap_writel(l, USB_TRANSCEIVER_CTRL);
    362	}
    363
    364	switch (nwires) {
    365	case 3:
    366		syscon1 = 2;
    367		break;
    368	case 4:
    369		syscon1 = 1;
    370		break;
    371	case 6:
    372		syscon1 = 3;
    373		{
    374			u32 l;
    375
    376			omap_cfg_reg(AA9_USB0_VP);
    377			omap_cfg_reg(R9_USB0_VM);
    378			l = omap_readl(USB_TRANSCEIVER_CTRL);
    379			l |= CONF_USB2_UNI_R;
    380			omap_writel(l, USB_TRANSCEIVER_CTRL);
    381		}
    382		break;
    383	default:
    384		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
    385			0, nwires);
    386	}
    387
    388	return syscon1 << 16;
    389}
    390
    391static u32 __init omap1_usb1_init(unsigned nwires)
    392{
    393	u32	syscon1 = 0;
    394
    395	if (!cpu_is_omap15xx() && nwires != 6) {
    396		u32 l;
    397
    398		l = omap_readl(USB_TRANSCEIVER_CTRL);
    399		l &= ~CONF_USB1_UNI_R;
    400		omap_writel(l, USB_TRANSCEIVER_CTRL);
    401	}
    402	if (nwires == 0)
    403		return 0;
    404
    405	/* external transceiver */
    406	omap_cfg_reg(USB1_TXD);
    407	omap_cfg_reg(USB1_TXEN);
    408	if (nwires != 3)
    409		omap_cfg_reg(USB1_RCV);
    410
    411	if (cpu_is_omap15xx()) {
    412		omap_cfg_reg(USB1_SEO);
    413		omap_cfg_reg(USB1_SPEED);
    414		// SUSP
    415	} else if (cpu_is_omap1610() || cpu_is_omap5912()) {
    416		omap_cfg_reg(W13_1610_USB1_SE0);
    417		omap_cfg_reg(R13_1610_USB1_SPEED);
    418		// SUSP
    419	} else if (cpu_is_omap1710()) {
    420		omap_cfg_reg(R13_1710_USB1_SE0);
    421		// SUSP
    422	} else {
    423		pr_debug("usb%d cpu unrecognized\n", 1);
    424		return 0;
    425	}
    426
    427	switch (nwires) {
    428	case 2:
    429		goto bad;
    430	case 3:
    431		syscon1 = 2;
    432		break;
    433	case 4:
    434		syscon1 = 1;
    435		break;
    436	case 6:
    437		syscon1 = 3;
    438		omap_cfg_reg(USB1_VP);
    439		omap_cfg_reg(USB1_VM);
    440		if (!cpu_is_omap15xx()) {
    441			u32 l;
    442
    443			l = omap_readl(USB_TRANSCEIVER_CTRL);
    444			l |= CONF_USB1_UNI_R;
    445			omap_writel(l, USB_TRANSCEIVER_CTRL);
    446		}
    447		break;
    448	default:
    449bad:
    450		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
    451			1, nwires);
    452	}
    453
    454	return syscon1 << 20;
    455}
    456
    457static u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
    458{
    459	u32	syscon1 = 0;
    460
    461	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
    462	if (alt_pingroup || nwires == 0)
    463		return 0;
    464
    465	if (!cpu_is_omap15xx() && nwires != 6) {
    466		u32 l;
    467
    468		l = omap_readl(USB_TRANSCEIVER_CTRL);
    469		l &= ~CONF_USB2_UNI_R;
    470		omap_writel(l, USB_TRANSCEIVER_CTRL);
    471	}
    472
    473	/* external transceiver */
    474	if (cpu_is_omap15xx()) {
    475		omap_cfg_reg(USB2_TXD);
    476		omap_cfg_reg(USB2_TXEN);
    477		omap_cfg_reg(USB2_SEO);
    478		if (nwires != 3)
    479			omap_cfg_reg(USB2_RCV);
    480		/* there is no USB2_SPEED */
    481	} else if (cpu_is_omap16xx()) {
    482		omap_cfg_reg(V6_USB2_TXD);
    483		omap_cfg_reg(W9_USB2_TXEN);
    484		omap_cfg_reg(W5_USB2_SE0);
    485		if (nwires != 3)
    486			omap_cfg_reg(Y5_USB2_RCV);
    487		// FIXME omap_cfg_reg(USB2_SPEED);
    488	} else {
    489		pr_debug("usb%d cpu unrecognized\n", 1);
    490		return 0;
    491	}
    492
    493	// omap_cfg_reg(USB2_SUSP);
    494
    495	switch (nwires) {
    496	case 2:
    497		goto bad;
    498	case 3:
    499		syscon1 = 2;
    500		break;
    501	case 4:
    502		syscon1 = 1;
    503		break;
    504	case 5:
    505		goto bad;
    506	case 6:
    507		syscon1 = 3;
    508		if (cpu_is_omap15xx()) {
    509			omap_cfg_reg(USB2_VP);
    510			omap_cfg_reg(USB2_VM);
    511		} else {
    512			u32 l;
    513
    514			omap_cfg_reg(AA9_USB2_VP);
    515			omap_cfg_reg(R9_USB2_VM);
    516			l = omap_readl(USB_TRANSCEIVER_CTRL);
    517			l |= CONF_USB2_UNI_R;
    518			omap_writel(l, USB_TRANSCEIVER_CTRL);
    519		}
    520		break;
    521	default:
    522bad:
    523		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
    524			2, nwires);
    525	}
    526
    527	return syscon1 << 24;
    528}
    529
    530#ifdef	CONFIG_ARCH_OMAP15XX
    531/* OMAP-1510 OHCI has its own MMU for DMA */
    532#define OMAP1510_LB_MEMSIZE	32	/* Should be same as SDRAM size */
    533#define OMAP1510_LB_CLOCK_DIV	0xfffec10c
    534#define OMAP1510_LB_MMU_CTL	0xfffec208
    535#define OMAP1510_LB_MMU_LCK	0xfffec224
    536#define OMAP1510_LB_MMU_LD_TLB	0xfffec228
    537#define OMAP1510_LB_MMU_CAM_H	0xfffec22c
    538#define OMAP1510_LB_MMU_CAM_L	0xfffec230
    539#define OMAP1510_LB_MMU_RAM_H	0xfffec234
    540#define OMAP1510_LB_MMU_RAM_L	0xfffec238
    541
    542/*
    543 * Bus address is physical address, except for OMAP-1510 Local Bus.
    544 * OMAP-1510 bus address is translated into a Local Bus address if the
    545 * OMAP bus type is lbus.
    546 */
    547#define OMAP1510_LB_OFFSET	   UL(0x30000000)
    548
    549/*
    550 * OMAP-1510 specific Local Bus clock on/off
    551 */
    552static int omap_1510_local_bus_power(int on)
    553{
    554	if (on) {
    555		omap_writel((1 << 1) | (1 << 0), OMAP1510_LB_MMU_CTL);
    556		udelay(200);
    557	} else {
    558		omap_writel(0, OMAP1510_LB_MMU_CTL);
    559	}
    560
    561	return 0;
    562}
    563
    564/*
    565 * OMAP-1510 specific Local Bus initialization
    566 * NOTE: This assumes 32MB memory size in OMAP1510LB_MEMSIZE.
    567 *       See also arch/mach-omap/memory.h for __virt_to_dma() and
    568 *       __dma_to_virt() which need to match with the physical
    569 *       Local Bus address below.
    570 */
    571static int omap_1510_local_bus_init(void)
    572{
    573	unsigned int tlb;
    574	unsigned long lbaddr, physaddr;
    575
    576	omap_writel((omap_readl(OMAP1510_LB_CLOCK_DIV) & 0xfffffff8) | 0x4,
    577	       OMAP1510_LB_CLOCK_DIV);
    578
    579	/* Configure the Local Bus MMU table */
    580	for (tlb = 0; tlb < OMAP1510_LB_MEMSIZE; tlb++) {
    581		lbaddr = tlb * 0x00100000 + OMAP1510_LB_OFFSET;
    582		physaddr = tlb * 0x00100000 + PHYS_OFFSET;
    583		omap_writel((lbaddr & 0x0fffffff) >> 22, OMAP1510_LB_MMU_CAM_H);
    584		omap_writel(((lbaddr & 0x003ffc00) >> 6) | 0xc,
    585		       OMAP1510_LB_MMU_CAM_L);
    586		omap_writel(physaddr >> 16, OMAP1510_LB_MMU_RAM_H);
    587		omap_writel((physaddr & 0x0000fc00) | 0x300, OMAP1510_LB_MMU_RAM_L);
    588		omap_writel(tlb << 4, OMAP1510_LB_MMU_LCK);
    589		omap_writel(0x1, OMAP1510_LB_MMU_LD_TLB);
    590	}
    591
    592	/* Enable the walking table */
    593	omap_writel(omap_readl(OMAP1510_LB_MMU_CTL) | (1 << 3), OMAP1510_LB_MMU_CTL);
    594	udelay(200);
    595
    596	return 0;
    597}
    598
    599static void omap_1510_local_bus_reset(void)
    600{
    601	omap_1510_local_bus_power(1);
    602	omap_1510_local_bus_init();
    603}
    604
    605/* ULPD_DPLL_CTRL */
    606#define DPLL_IOB		(1 << 13)
    607#define DPLL_PLL_ENABLE		(1 << 4)
    608#define DPLL_LOCK		(1 << 0)
    609
    610/* ULPD_APLL_CTRL */
    611#define APLL_NDPLL_SWITCH	(1 << 0)
    612
    613static void __init omap_1510_usb_init(struct omap_usb_config *config)
    614{
    615	unsigned int val;
    616	u16 w;
    617
    618	config->usb0_init(config->pins[0], is_usb0_device(config));
    619	config->usb1_init(config->pins[1]);
    620	config->usb2_init(config->pins[2], 0);
    621
    622	val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
    623	val |= (config->hmc_mode << 1);
    624	omap_writel(val, MOD_CONF_CTRL_0);
    625
    626	printk("USB: hmc %d", config->hmc_mode);
    627	if (config->pins[0])
    628		pr_cont(", usb0 %d wires%s", config->pins[0],
    629			is_usb0_device(config) ? " (dev)" : "");
    630	if (config->pins[1])
    631		pr_cont(", usb1 %d wires", config->pins[1]);
    632	if (config->pins[2])
    633		pr_cont(", usb2 %d wires", config->pins[2]);
    634	pr_cont("\n");
    635
    636	/* use DPLL for 48 MHz function clock */
    637	pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
    638			omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
    639
    640	w = omap_readw(ULPD_APLL_CTRL);
    641	w &= ~APLL_NDPLL_SWITCH;
    642	omap_writew(w, ULPD_APLL_CTRL);
    643
    644	w = omap_readw(ULPD_DPLL_CTRL);
    645	w |= DPLL_IOB | DPLL_PLL_ENABLE;
    646	omap_writew(w, ULPD_DPLL_CTRL);
    647
    648	w = omap_readw(ULPD_SOFT_REQ);
    649	w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
    650	omap_writew(w, ULPD_SOFT_REQ);
    651
    652	while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
    653		cpu_relax();
    654
    655#if IS_ENABLED(CONFIG_USB_OMAP)
    656	if (config->register_dev) {
    657		int status;
    658
    659		udc_device.dev.platform_data = config;
    660		status = platform_device_register(&udc_device);
    661		if (status)
    662			pr_debug("can't register UDC device, %d\n", status);
    663		/* udc driver gates 48MHz by D+ pullup */
    664	}
    665#endif
    666
    667	if (IS_ENABLED(CONFIG_USB_OHCI_HCD) && config->register_host) {
    668		int status;
    669
    670		ohci_device.dev.platform_data = config;
    671		dma_direct_set_offset(&ohci_device.dev, PHYS_OFFSET,
    672				      OMAP1510_LB_OFFSET, (u64)-1);
    673		status = platform_device_register(&ohci_device);
    674		if (status)
    675			pr_debug("can't register OHCI device, %d\n", status);
    676		/* hcd explicitly gates 48MHz */
    677
    678		config->lb_reset = omap_1510_local_bus_reset;
    679	}
    680}
    681
    682#else
    683static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
    684#endif
    685
    686void __init omap1_usb_init(struct omap_usb_config *_pdata)
    687{
    688	struct omap_usb_config *pdata;
    689
    690	pdata = kmemdup(_pdata, sizeof(*pdata), GFP_KERNEL);
    691	if (!pdata)
    692		return;
    693
    694	pdata->usb0_init = omap1_usb0_init;
    695	pdata->usb1_init = omap1_usb1_init;
    696	pdata->usb2_init = omap1_usb2_init;
    697	udc_device_init(pdata);
    698	ohci_device_init(pdata);
    699	otg_device_init(pdata);
    700
    701	if (cpu_is_omap7xx() || cpu_is_omap16xx())
    702		omap_otg_init(pdata);
    703	else if (cpu_is_omap15xx())
    704		omap_1510_usb_init(pdata);
    705	else
    706		printk(KERN_ERR "USB: No init for your chip yet\n");
    707}