clockdomains33xx_data.c (5533B)
1/* 2 * AM33XX Clock Domain data. 3 * 4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 5 * Vaibhav Hiremath <hvaibhav@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17#include <linux/kernel.h> 18#include <linux/io.h> 19 20#include "clockdomain.h" 21#include "cm.h" 22#include "cm33xx.h" 23#include "cm-regbits-33xx.h" 24 25static struct clockdomain l4ls_am33xx_clkdm = { 26 .name = "l4ls_clkdm", 27 .pwrdm = { .name = "per_pwrdm" }, 28 .cm_inst = AM33XX_CM_PER_MOD, 29 .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET, 30 .flags = CLKDM_CAN_SWSUP, 31}; 32 33static struct clockdomain l3s_am33xx_clkdm = { 34 .name = "l3s_clkdm", 35 .pwrdm = { .name = "per_pwrdm" }, 36 .cm_inst = AM33XX_CM_PER_MOD, 37 .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET, 38 .flags = CLKDM_CAN_SWSUP, 39}; 40 41static struct clockdomain l4fw_am33xx_clkdm = { 42 .name = "l4fw_clkdm", 43 .pwrdm = { .name = "per_pwrdm" }, 44 .cm_inst = AM33XX_CM_PER_MOD, 45 .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET, 46 .flags = CLKDM_CAN_SWSUP, 47}; 48 49static struct clockdomain l3_am33xx_clkdm = { 50 .name = "l3_clkdm", 51 .pwrdm = { .name = "per_pwrdm" }, 52 .cm_inst = AM33XX_CM_PER_MOD, 53 .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET, 54 .flags = CLKDM_CAN_SWSUP, 55}; 56 57static struct clockdomain l4hs_am33xx_clkdm = { 58 .name = "l4hs_clkdm", 59 .pwrdm = { .name = "per_pwrdm" }, 60 .cm_inst = AM33XX_CM_PER_MOD, 61 .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET, 62 .flags = CLKDM_CAN_SWSUP, 63}; 64 65static struct clockdomain ocpwp_l3_am33xx_clkdm = { 66 .name = "ocpwp_l3_clkdm", 67 .pwrdm = { .name = "per_pwrdm" }, 68 .cm_inst = AM33XX_CM_PER_MOD, 69 .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET, 70 .flags = CLKDM_CAN_SWSUP, 71}; 72 73static struct clockdomain pruss_ocp_am33xx_clkdm = { 74 .name = "pruss_ocp_clkdm", 75 .pwrdm = { .name = "per_pwrdm" }, 76 .cm_inst = AM33XX_CM_PER_MOD, 77 .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET, 78 .flags = CLKDM_CAN_SWSUP, 79}; 80 81static struct clockdomain cpsw_125mhz_am33xx_clkdm = { 82 .name = "cpsw_125mhz_clkdm", 83 .pwrdm = { .name = "per_pwrdm" }, 84 .cm_inst = AM33XX_CM_PER_MOD, 85 .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET, 86 .flags = CLKDM_CAN_SWSUP, 87}; 88 89static struct clockdomain lcdc_am33xx_clkdm = { 90 .name = "lcdc_clkdm", 91 .pwrdm = { .name = "per_pwrdm" }, 92 .cm_inst = AM33XX_CM_PER_MOD, 93 .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET, 94 .flags = CLKDM_CAN_SWSUP, 95}; 96 97static struct clockdomain clk_24mhz_am33xx_clkdm = { 98 .name = "clk_24mhz_clkdm", 99 .pwrdm = { .name = "per_pwrdm" }, 100 .cm_inst = AM33XX_CM_PER_MOD, 101 .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET, 102 .flags = CLKDM_CAN_SWSUP, 103}; 104 105static struct clockdomain l4_wkup_am33xx_clkdm = { 106 .name = "l4_wkup_clkdm", 107 .pwrdm = { .name = "wkup_pwrdm" }, 108 .cm_inst = AM33XX_CM_WKUP_MOD, 109 .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET, 110 .flags = CLKDM_CAN_SWSUP, 111}; 112 113static struct clockdomain l3_aon_am33xx_clkdm = { 114 .name = "l3_aon_clkdm", 115 .pwrdm = { .name = "wkup_pwrdm" }, 116 .cm_inst = AM33XX_CM_WKUP_MOD, 117 .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET, 118 .flags = CLKDM_CAN_SWSUP, 119}; 120 121static struct clockdomain l4_wkup_aon_am33xx_clkdm = { 122 .name = "l4_wkup_aon_clkdm", 123 .pwrdm = { .name = "wkup_pwrdm" }, 124 .cm_inst = AM33XX_CM_WKUP_MOD, 125 .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET, 126 .flags = CLKDM_CAN_SWSUP, 127}; 128 129static struct clockdomain mpu_am33xx_clkdm = { 130 .name = "mpu_clkdm", 131 .pwrdm = { .name = "mpu_pwrdm" }, 132 .cm_inst = AM33XX_CM_MPU_MOD, 133 .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET, 134 .flags = CLKDM_CAN_SWSUP, 135}; 136 137static struct clockdomain l4_rtc_am33xx_clkdm = { 138 .name = "l4_rtc_clkdm", 139 .pwrdm = { .name = "rtc_pwrdm" }, 140 .cm_inst = AM33XX_CM_RTC_MOD, 141 .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET, 142 .flags = CLKDM_CAN_SWSUP, 143}; 144 145static struct clockdomain gfx_l3_am33xx_clkdm = { 146 .name = "gfx_l3_clkdm", 147 .pwrdm = { .name = "gfx_pwrdm" }, 148 .cm_inst = AM33XX_CM_GFX_MOD, 149 .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET, 150 .flags = CLKDM_CAN_SWSUP, 151}; 152 153static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = { 154 .name = "gfx_l4ls_gfx_clkdm", 155 .pwrdm = { .name = "gfx_pwrdm" }, 156 .cm_inst = AM33XX_CM_GFX_MOD, 157 .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET, 158 .flags = CLKDM_CAN_SWSUP, 159}; 160 161static struct clockdomain l4_cefuse_am33xx_clkdm = { 162 .name = "l4_cefuse_clkdm", 163 .pwrdm = { .name = "cefuse_pwrdm" }, 164 .cm_inst = AM33XX_CM_CEFUSE_MOD, 165 .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET, 166 .flags = CLKDM_CAN_SWSUP, 167}; 168 169static struct clockdomain *clockdomains_am33xx[] __initdata = { 170 &l4ls_am33xx_clkdm, 171 &l3s_am33xx_clkdm, 172 &l4fw_am33xx_clkdm, 173 &l3_am33xx_clkdm, 174 &l4hs_am33xx_clkdm, 175 &ocpwp_l3_am33xx_clkdm, 176 &pruss_ocp_am33xx_clkdm, 177 &cpsw_125mhz_am33xx_clkdm, 178 &lcdc_am33xx_clkdm, 179 &clk_24mhz_am33xx_clkdm, 180 &l4_wkup_am33xx_clkdm, 181 &l3_aon_am33xx_clkdm, 182 &l4_wkup_aon_am33xx_clkdm, 183 &mpu_am33xx_clkdm, 184 &l4_rtc_am33xx_clkdm, 185 &gfx_l3_am33xx_clkdm, 186 &gfx_l4ls_gfx_am33xx_clkdm, 187 &l4_cefuse_am33xx_clkdm, 188 NULL, 189}; 190 191void __init am33xx_clockdomains_init(void) 192{ 193 clkdm_register_platform_funcs(&am33xx_clkdm_operations); 194 clkdm_register_clkdms(clockdomains_am33xx); 195 clkdm_complete_init(); 196}