cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cm1_54xx.h (1369B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * OMAP54xx CM1 instance offset macros
      4 *
      5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
      6 *
      7 * Paul Walmsley (paul@pwsan.com)
      8 * Rajendra Nayak (rnayak@ti.com)
      9 * Benoit Cousson (b-cousson@ti.com)
     10 *
     11 * This file is automatically generated from the OMAP hardware databases.
     12 * We respectfully ask that any modifications to this file be coordinated
     13 * with the public linux-omap@vger.kernel.org mailing list and the
     14 * authors above to ensure that the autogeneration scripts are kept
     15 * up-to-date with the file contents.
     16 */
     17
     18#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
     19#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
     20
     21/* CM1 base address */
     22#define OMAP54XX_CM_CORE_AON_BASE		0x4a004000
     23
     24#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg)				\
     25	OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
     26
     27/* CM_CORE_AON instances */
     28#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
     29#define OMAP54XX_CM_CORE_AON_CKGEN_INST		0x0100
     30#define OMAP54XX_CM_CORE_AON_MPU_INST		0x0300
     31#define OMAP54XX_CM_CORE_AON_DSP_INST		0x0400
     32#define OMAP54XX_CM_CORE_AON_ABE_INST		0x0500
     33
     34/* CM_CORE_AON clockdomain register offsets (from instance start) */
     35#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
     36#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS	0x0000
     37#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS	0x0000
     38
     39#endif