cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq.c (1236B)

      1/*
      2 * arch/arm/mach-orion5x/irq.c
      3 *
      4 * Core IRQ functions for Marvell Orion System On Chip
      5 *
      6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
      7 *
      8 * This file is licensed under the terms of the GNU General Public
      9 * License version 2.  This program is licensed "as is" without any
     10 * warranty of any kind, whether express or implied.
     11 */
     12#include <linux/gpio.h>
     13#include <linux/kernel.h>
     14#include <linux/irq.h>
     15#include <linux/io.h>
     16#include <plat/orion-gpio.h>
     17#include <plat/irq.h>
     18#include <asm/exception.h>
     19#include "bridge-regs.h"
     20#include "common.h"
     21
     22static int __initdata gpio0_irqs[4] = {
     23	IRQ_ORION5X_GPIO_0_7,
     24	IRQ_ORION5X_GPIO_8_15,
     25	IRQ_ORION5X_GPIO_16_23,
     26	IRQ_ORION5X_GPIO_24_31,
     27};
     28
     29static asmlinkage void
     30__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
     31{
     32	u32 stat;
     33
     34	stat = readl_relaxed(MAIN_IRQ_CAUSE);
     35	stat &= readl_relaxed(MAIN_IRQ_MASK);
     36	if (stat) {
     37		unsigned int hwirq = 1 + __fls(stat);
     38		handle_IRQ(hwirq, regs);
     39		return;
     40	}
     41}
     42
     43void __init orion5x_init_irq(void)
     44{
     45	orion_irq_init(1, MAIN_IRQ_MASK);
     46
     47	set_handle_irq(orion5x_legacy_handle_irq);
     48
     49	/*
     50	 * Initialize gpiolib for GPIOs 0-31.
     51	 */
     52	orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0,
     53			IRQ_ORION5X_GPIO_START, gpio0_irqs);
     54}