cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mpp.h (5858B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef __ARCH_ORION5X_MPP_H
      3#define __ARCH_ORION5X_MPP_H
      4
      5#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
      6	/* MPP number */		((_num) & 0xff) | \
      7	/* MPP select value */		(((_sel) & 0xf) << 8) | \
      8	/* may be input signal */	((!!(_in)) << 12) | \
      9	/* may be output signal */	((!!(_out)) << 13) | \
     10	/* available on F5181l */	((!!(_F5181l)) << 14) | \
     11	/* available on F5182 */	((!!(_F5182)) << 15) | \
     12	/* available on F5281 */	((!!(_F5281)) << 16))
     13
     14				/* num sel  i  o  5181 5182 5281 */
     15
     16#define MPP_F5181_MASK		MPP(0,  0x0, 0, 0, 1,   0,   0)
     17#define MPP_F5182_MASK		MPP(0,  0x0, 0, 0, 0,   1,   0)
     18#define MPP_F5281_MASK		MPP(0,  0x0, 0, 0, 0,   0,   1)
     19
     20#define MPP0_UNUSED	        MPP(0,  0x3, 0, 0, 1,   1,   1)
     21#define MPP0_GPIO		MPP(0,  0x3, 1, 1, 1,   1,   1)
     22#define MPP0_PCIE_RST_OUTn	MPP(0,  0x0, 0, 0, 1,   1,   1)
     23#define MPP0_PCI_ARB            MPP(0,  0x2, 0, 0, 1,   1,   1)
     24
     25#define MPP1_UNUSED		MPP(1,  0x0, 0, 0, 1,   1,   1)
     26#define MPP1_GPIO		MPP(1,  0x0, 1, 1, 1,   1,   1)
     27#define MPP1_PCI_ARB            MPP(1,  0x2, 0, 0, 1,   1,   1)
     28
     29#define MPP2_UNUSED		MPP(2,  0x0, 0, 0, 1,   1,   1)
     30#define MPP2_GPIO		MPP(2,  0x0, 1, 1, 1,   1,   1)
     31#define MPP2_PCI_ARB            MPP(2,  0x2, 0, 0, 1,   1,   1)
     32#define MPP2_PCI_PMEn           MPP(2,  0x3, 0, 0, 1,   1,   1)
     33
     34#define MPP3_UNUSED		MPP(3,  0x0, 0, 0, 1,   1,   1)
     35#define MPP3_GPIO		MPP(3,  0x0, 1, 1, 1,   1,   1)
     36#define MPP3_PCI_ARB            MPP(3,  0x2, 0, 0, 1,   1,   1)
     37
     38#define MPP4_UNUSED		MPP(4,  0x0, 0, 0, 1,   1,   1)
     39#define MPP4_GPIO		MPP(4,  0x0, 1, 1, 1,   1,   1)
     40#define MPP4_PCI_ARB            MPP(4,  0x2, 0, 0, 1,   1,   1)
     41#define MPP4_NAND               MPP(4,  0x4, 0, 0, 0,   1,   1)
     42#define MPP4_SATA_LED           MPP(4,  0x5, 0, 0, 0,   1,   0)
     43
     44#define MPP5_UNUSED		MPP(5,  0x0, 0, 0, 1,   1,   1)
     45#define MPP5_GPIO		MPP(5,  0x0, 1, 1, 1,   1,   1)
     46#define MPP5_PCI_ARB            MPP(5,  0x2, 0, 0, 1,   1,   1)
     47#define MPP5_NAND               MPP(5,  0x4, 0, 0, 0,   1,   1)
     48#define MPP5_SATA_LED           MPP(5,  0x5, 0, 0, 0,   1,   0)
     49
     50#define MPP6_UNUSED		MPP(6,  0x0, 0, 0, 1,   1,   1)
     51#define MPP6_GPIO		MPP(6,  0x0, 1, 1, 1,   1,   1)
     52#define MPP6_PCI_ARB            MPP(6,  0x2, 0, 0, 1,   1,   1)
     53#define MPP6_NAND               MPP(6,  0x4, 0, 0, 0,   1,   1)
     54#define MPP6_PCI_CLK            MPP(6,  0x5, 0, 0, 1,   0,   0)
     55#define MPP6_SATA_LED           MPP(6,  0x5, 0, 0, 0,   1,   0)
     56
     57#define MPP7_UNUSED		MPP(7,  0x0, 0, 0, 1,   1,   1)
     58#define MPP7_GPIO		MPP(7,  0x0, 1, 1, 1,   1,   1)
     59#define MPP7_PCI_ARB            MPP(7,  0x2, 0, 0, 1,   1,   1)
     60#define MPP7_NAND               MPP(7,  0x4, 0, 0, 0,   1,   1)
     61#define MPP7_PCI_CLK            MPP(7,  0x5, 0, 0, 1,   0,   0)
     62#define MPP7_SATA_LED           MPP(7,  0x5, 0, 0, 0,   1,   0)
     63
     64#define MPP8_UNUSED		MPP(8,  0x0, 0, 0, 1,   1,   1)
     65#define MPP8_GPIO		MPP(8,  0x0, 1, 1, 1,   1,   1)
     66#define MPP8_GIGE               MPP(8,  0x1, 0, 0, 1,   1,   1)
     67
     68#define MPP9_UNUSED		MPP(9,  0x0, 0, 0, 1,   1,   1)
     69#define MPP9_GPIO		MPP(9,  0x0, 1, 1, 1,   1,   1)
     70#define MPP9_GIGE               MPP(9,  0x1, 0, 0, 1,   1,   1)
     71
     72#define MPP10_UNUSED		MPP(10, 0x0, 0, 0, 1,   1,   1)
     73#define MPP10_GPIO		MPP(10, 0x0, 1, 1, 1,   1,   1)
     74#define MPP10_GIGE              MPP(10, 0x1, 0, 0, 1,   1,   1)
     75
     76#define MPP11_UNUSED		MPP(11, 0x0, 0, 0, 1,   1,   1)
     77#define MPP11_GPIO		MPP(11, 0x0, 1, 1, 1,   1,   1)
     78#define MPP11_GIGE              MPP(11, 0x1, 0, 0, 1,   1,   1)
     79
     80#define MPP12_UNUSED		MPP(12, 0x0, 0, 0, 1,   1,   1)
     81#define MPP12_GPIO		MPP(12, 0x0, 1, 1, 1,   1,   1)
     82#define MPP12_GIGE              MPP(12, 0x1, 0, 0, 1,   1,   1)
     83#define MPP12_NAND              MPP(12, 0x4, 0, 0, 0,   1,   1)
     84#define MPP12_SATA_LED          MPP(12, 0x5, 0, 0, 0,   1,   0)
     85
     86#define MPP13_UNUSED		MPP(13, 0x0, 0, 0, 1,   1,   1)
     87#define MPP13_GPIO		MPP(13, 0x0, 1, 1, 1,   1,   1)
     88#define MPP13_GIGE              MPP(13, 0x1, 0, 0, 1,   1,   1)
     89#define MPP13_NAND              MPP(13, 0x4, 0, 0, 0,   1,   1)
     90#define MPP13_SATA_LED          MPP(13, 0x5, 0, 0, 0,   1,   0)
     91
     92#define MPP14_UNUSED		MPP(14, 0x0, 0, 0, 1,   1,   1)
     93#define MPP14_GPIO		MPP(14, 0x0, 1, 1, 1,   1,   1)
     94#define MPP14_GIGE              MPP(14, 0x1, 0, 0, 1,   1,   1)
     95#define MPP14_NAND              MPP(14, 0x4, 0, 0, 0,   1,   1)
     96#define MPP14_SATA_LED          MPP(14, 0x5, 0, 0, 0,   1,   0)
     97
     98#define MPP15_UNUSED		MPP(15, 0x0, 0, 0, 1,   1,   1)
     99#define MPP15_GPIO		MPP(15, 0x0, 1, 1, 1,   1,   1)
    100#define MPP15_GIGE              MPP(15, 0x1, 0, 0, 1,   1,   1)
    101#define MPP15_NAND              MPP(15, 0x4, 0, 0, 0,   1,   1)
    102#define MPP15_SATA_LED          MPP(15, 0x5, 0, 0, 0,   1,   0)
    103
    104#define MPP16_UNUSED		MPP(16, 0x0, 0, 0, 1,   1,   1)
    105#define MPP16_GPIO		MPP(16, 0x5, 1, 1, 0,   1,   0)
    106#define MPP16_GIGE              MPP(16, 0x1, 0, 0, 1,   1,   1)
    107#define MPP16_NAND              MPP(16, 0x4, 0, 0, 0,   1,   1)
    108#define MPP16_UART              MPP(16, 0x0, 0, 0, 0,   1,   1)
    109
    110#define MPP17_UNUSED		MPP(17, 0x0, 0, 0, 1,   1,   1)
    111#define MPP17_GPIO		MPP(17, 0x5, 1, 1, 0,   1,   0)
    112#define MPP17_GIGE              MPP(17, 0x1, 0, 0, 1,   1,   1)
    113#define MPP17_NAND              MPP(17, 0x4, 0, 0, 0,   1,   1)
    114#define MPP17_UART              MPP(17, 0x0, 0, 0, 0,   1,   1)
    115
    116#define MPP18_UNUSED		MPP(18, 0x0, 0, 0, 1,   1,   1)
    117#define MPP18_GPIO		MPP(18, 0x5, 1, 1, 0,   1,   0)
    118#define MPP18_GIGE              MPP(18, 0x1, 0, 0, 1,   1,   1)
    119#define MPP18_UART              MPP(18, 0x0, 0, 0, 0,   1,   1)
    120
    121#define MPP19_UNUSED		MPP(19, 0x0, 0, 0, 1,   1,   1)
    122#define MPP19_GPIO		MPP(19, 0x5, 1, 1, 0,   1,   0)
    123#define MPP19_GIGE              MPP(19, 0x1, 0, 0, 1,   1,   1)
    124#define MPP19_UART              MPP(19, 0x0, 0, 0, 0,   1,   1)
    125
    126#define MPP_MAX			19
    127
    128void orion5x_mpp_conf(unsigned int *mpp_list);
    129
    130#endif