cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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wrt350n-v2-setup.c (6125B)


      1/*
      2 * arch/arm/mach-orion5x/wrt350n-v2-setup.c
      3 *
      4 * This file is licensed under the terms of the GNU General Public
      5 * License version 2.  This program is licensed "as is" without any
      6 * warranty of any kind, whether express or implied.
      7 */
      8#include <linux/gpio.h>
      9#include <linux/kernel.h>
     10#include <linux/init.h>
     11#include <linux/platform_device.h>
     12#include <linux/pci.h>
     13#include <linux/irq.h>
     14#include <linux/delay.h>
     15#include <linux/mtd/physmap.h>
     16#include <linux/mv643xx_eth.h>
     17#include <linux/ethtool.h>
     18#include <linux/leds.h>
     19#include <linux/gpio_keys.h>
     20#include <linux/input.h>
     21#include <linux/platform_data/dsa.h>
     22#include <asm/mach-types.h>
     23#include <asm/mach/arch.h>
     24#include <asm/mach/pci.h>
     25#include "orion5x.h"
     26#include "common.h"
     27#include "mpp.h"
     28
     29/*
     30 * LEDs attached to GPIO
     31 */
     32static struct gpio_led wrt350n_v2_led_pins[] = {
     33	{
     34		.name		= "wrt350nv2:green:power",
     35		.gpio		= 0,
     36		.active_low	= 1,
     37	}, {
     38		.name		= "wrt350nv2:green:security",
     39		.gpio		= 1,
     40		.active_low	= 1,
     41	}, {
     42		.name		= "wrt350nv2:orange:power",
     43		.gpio		= 5,
     44		.active_low	= 1,
     45	}, {
     46		.name		= "wrt350nv2:green:usb",
     47		.gpio		= 6,
     48		.active_low	= 1,
     49	}, {
     50		.name		= "wrt350nv2:green:wireless",
     51		.gpio		= 7,
     52		.active_low	= 1,
     53	},
     54};
     55
     56static struct gpio_led_platform_data wrt350n_v2_led_data = {
     57	.leds		= wrt350n_v2_led_pins,
     58	.num_leds	= ARRAY_SIZE(wrt350n_v2_led_pins),
     59};
     60
     61static struct platform_device wrt350n_v2_leds = {
     62	.name	= "leds-gpio",
     63	.id	= -1,
     64	.dev	= {
     65		.platform_data	= &wrt350n_v2_led_data,
     66	},
     67};
     68
     69/*
     70 * Buttons attached to GPIO
     71 */
     72static struct gpio_keys_button wrt350n_v2_buttons[] = {
     73	{
     74		.code		= KEY_RESTART,
     75		.gpio		= 3,
     76		.desc		= "Reset Button",
     77		.active_low	= 1,
     78	}, {
     79		.code		= KEY_WPS_BUTTON,
     80		.gpio		= 2,
     81		.desc		= "WPS Button",
     82		.active_low	= 1,
     83	},
     84};
     85
     86static struct gpio_keys_platform_data wrt350n_v2_button_data = {
     87	.buttons	= wrt350n_v2_buttons,
     88	.nbuttons	= ARRAY_SIZE(wrt350n_v2_buttons),
     89};
     90
     91static struct platform_device wrt350n_v2_button_device = {
     92	.name		= "gpio-keys",
     93	.id		= -1,
     94	.num_resources	= 0,
     95	.dev		= {
     96		.platform_data	= &wrt350n_v2_button_data,
     97	},
     98};
     99
    100/*
    101 * General setup
    102 */
    103static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
    104	MPP0_GPIO,		/* Power LED green (0=on) */
    105	MPP1_GPIO,		/* Security LED (0=on) */
    106	MPP2_GPIO,		/* Internal Button (0=on) */
    107	MPP3_GPIO,		/* Reset Button (0=on) */
    108	MPP4_GPIO,		/* PCI int */
    109	MPP5_GPIO,		/* Power LED orange (0=on) */
    110	MPP6_GPIO,		/* USB LED (0=on) */
    111	MPP7_GPIO,		/* Wireless LED (0=on) */
    112	MPP8_UNUSED,		/* ??? */
    113	MPP9_GIGE,		/* GE_RXERR */
    114	MPP10_UNUSED,		/* ??? */
    115	MPP11_UNUSED,		/* ??? */
    116	MPP12_GIGE,		/* GE_TXD[4] */
    117	MPP13_GIGE,		/* GE_TXD[5] */
    118	MPP14_GIGE,		/* GE_TXD[6] */
    119	MPP15_GIGE,		/* GE_TXD[7] */
    120	MPP16_GIGE,		/* GE_RXD[4] */
    121	MPP17_GIGE,		/* GE_RXD[5] */
    122	MPP18_GIGE,		/* GE_RXD[6] */
    123	MPP19_GIGE,		/* GE_RXD[7] */
    124	0,
    125};
    126
    127/*
    128 * 8M NOR flash Device bus boot chip select
    129 */
    130#define WRT350N_V2_NOR_BOOT_BASE	0xf4000000
    131#define WRT350N_V2_NOR_BOOT_SIZE	SZ_8M
    132
    133static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
    134	{
    135		.name		= "kernel",
    136		.offset		= 0x00000000,
    137		.size		= 0x00760000,
    138	}, {
    139		.name		= "rootfs",
    140		.offset		= 0x001a0000,
    141		.size		= 0x005c0000,
    142	}, {
    143		.name		= "lang",
    144		.offset		= 0x00760000,
    145		.size		= 0x00040000,
    146	}, {
    147		.name		= "nvram",
    148		.offset		= 0x007a0000,
    149		.size		= 0x00020000,
    150	}, {
    151		.name		= "u-boot",
    152		.offset		= 0x007c0000,
    153		.size		= 0x00040000,
    154	},
    155};
    156
    157static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
    158	.width		= 1,
    159	.parts		= wrt350n_v2_nor_flash_partitions,
    160	.nr_parts	= ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
    161};
    162
    163static struct resource wrt350n_v2_nor_flash_resource = {
    164	.flags		= IORESOURCE_MEM,
    165	.start		= WRT350N_V2_NOR_BOOT_BASE,
    166	.end		= WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
    167};
    168
    169static struct platform_device wrt350n_v2_nor_flash = {
    170	.name			= "physmap-flash",
    171	.id			= 0,
    172	.dev		= {
    173		.platform_data	= &wrt350n_v2_nor_flash_data,
    174	},
    175	.num_resources		= 1,
    176	.resource		= &wrt350n_v2_nor_flash_resource,
    177};
    178
    179static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
    180	.phy_addr	= MV643XX_ETH_PHY_NONE,
    181	.speed		= SPEED_1000,
    182	.duplex		= DUPLEX_FULL,
    183};
    184
    185static struct dsa_chip_data wrt350n_v2_switch_chip_data = {
    186	.port_names[0]	= "lan2",
    187	.port_names[1]	= "lan1",
    188	.port_names[2]	= "wan",
    189	.port_names[3]	= "cpu",
    190	.port_names[5]	= "lan3",
    191	.port_names[7]	= "lan4",
    192};
    193
    194static void __init wrt350n_v2_init(void)
    195{
    196	/*
    197	 * Setup basic Orion functions. Need to be called early.
    198	 */
    199	orion5x_init();
    200
    201	orion5x_mpp_conf(wrt350n_v2_mpp_modes);
    202
    203	/*
    204	 * Configure peripherals.
    205	 */
    206	orion5x_ehci0_init();
    207	orion5x_eth_init(&wrt350n_v2_eth_data);
    208	orion5x_eth_switch_init(&wrt350n_v2_switch_chip_data);
    209	orion5x_uart0_init();
    210
    211	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
    212				    ORION_MBUS_DEVBUS_BOOT_ATTR,
    213				    WRT350N_V2_NOR_BOOT_BASE,
    214				    WRT350N_V2_NOR_BOOT_SIZE);
    215	platform_device_register(&wrt350n_v2_nor_flash);
    216	platform_device_register(&wrt350n_v2_leds);
    217	platform_device_register(&wrt350n_v2_button_device);
    218}
    219
    220static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot,
    221	u8 pin)
    222{
    223	int irq;
    224
    225	/*
    226	 * Check for devices with hard-wired IRQs.
    227	 */
    228	irq = orion5x_pci_map_irq(dev, slot, pin);
    229	if (irq != -1)
    230		return irq;
    231
    232	/*
    233	 * Mini-PCI slot.
    234	 */
    235	if (slot == 7)
    236		return gpio_to_irq(4);
    237
    238	return -1;
    239}
    240
    241static struct hw_pci wrt350n_v2_pci __initdata = {
    242	.nr_controllers	= 2,
    243	.setup		= orion5x_pci_sys_setup,
    244	.scan		= orion5x_pci_sys_scan_bus,
    245	.map_irq	= wrt350n_v2_pci_map_irq,
    246};
    247
    248static int __init wrt350n_v2_pci_init(void)
    249{
    250	if (machine_is_wrt350n_v2())
    251		pci_common_init(&wrt350n_v2_pci);
    252
    253	return 0;
    254}
    255subsys_initcall(wrt350n_v2_pci_init);
    256
    257MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
    258	/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
    259	.atag_offset	= 0x100,
    260	.nr_irqs	= ORION5X_NR_IRQS,
    261	.init_machine	= wrt350n_v2_init,
    262	.map_io		= orion5x_map_io,
    263	.init_early	= orion5x_init_early,
    264	.init_irq	= orion5x_init_irq,
    265	.init_time	= orion5x_timer_init,
    266	.fixup		= tag_fixup_mem32,
    267	.restart	= orion5x_restart,
    268MACHINE_END