cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

reset.c (2002B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2#include <linux/kernel.h>
      3#include <linux/module.h>
      4#include <linux/delay.h>
      5#include <linux/gpio.h>
      6#include <linux/io.h>
      7#include <asm/proc-fns.h>
      8#include <asm/system_misc.h>
      9
     10#include "regs-ost.h"
     11#include "reset.h"
     12#include "smemc.h"
     13
     14static void do_hw_reset(void);
     15
     16static int reset_gpio = -1;
     17
     18int init_gpio_reset(int gpio, int output, int level)
     19{
     20	int rc;
     21
     22	rc = gpio_request(gpio, "reset generator");
     23	if (rc) {
     24		printk(KERN_ERR "Can't request reset_gpio\n");
     25		goto out;
     26	}
     27
     28	if (output)
     29		rc = gpio_direction_output(gpio, level);
     30	else
     31		rc = gpio_direction_input(gpio);
     32	if (rc) {
     33		printk(KERN_ERR "Can't configure reset_gpio\n");
     34		gpio_free(gpio);
     35		goto out;
     36	}
     37
     38out:
     39	if (!rc)
     40		reset_gpio = gpio;
     41
     42	return rc;
     43}
     44
     45/*
     46 * Trigger GPIO reset.
     47 * This covers various types of logic connecting gpio pin
     48 * to RESET pins (nRESET or GPIO_RESET):
     49 */
     50static void do_gpio_reset(void)
     51{
     52	BUG_ON(reset_gpio == -1);
     53
     54	/* drive it low */
     55	gpio_direction_output(reset_gpio, 0);
     56	mdelay(2);
     57	/* rising edge or drive high */
     58	gpio_set_value(reset_gpio, 1);
     59	mdelay(2);
     60	/* falling edge */
     61	gpio_set_value(reset_gpio, 0);
     62
     63	/* give it some time */
     64	mdelay(10);
     65
     66	WARN_ON(1);
     67	/* fallback */
     68	do_hw_reset();
     69}
     70
     71static void do_hw_reset(void)
     72{
     73	/* Initialize the watchdog and let it fire */
     74	writel_relaxed(OWER_WME, OWER);
     75	writel_relaxed(OSSR_M3, OSSR);
     76	/* ... in 100 ms */
     77	writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
     78	/*
     79	 * SDRAM hangs on watchdog reset on Marvell PXA270 (erratum 71)
     80	 * we put SDRAM into self-refresh to prevent that
     81	 */
     82	while (1)
     83		writel_relaxed(MDREFR_SLFRSH, MDREFR);
     84}
     85
     86void pxa_restart(enum reboot_mode mode, const char *cmd)
     87{
     88	local_irq_disable();
     89	local_fiq_disable();
     90
     91	clear_reset_status(RESET_STATUS_ALL);
     92
     93	switch (mode) {
     94	case REBOOT_SOFT:
     95		/* Jump into ROM at address 0 */
     96		soft_restart(0);
     97		break;
     98	case REBOOT_GPIO:
     99		do_gpio_reset();
    100		break;
    101	case REBOOT_HARD:
    102	default:
    103		do_hw_reset();
    104		break;
    105	}
    106}