cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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smemc.h (4089B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Static memory controller register definitions for PXA CPUs
      4 *
      5 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
      6 */
      7
      8#ifndef __SMEMC_REGS_H
      9#define __SMEMC_REGS_H
     10
     11#define PXA2XX_SMEMC_BASE	0x48000000
     12#define PXA3XX_SMEMC_BASE	0x4a000000
     13#define SMEMC_VIRT		IOMEM(0xf6000000)
     14
     15#define MDCNFG		(SMEMC_VIRT + 0x00)  /* SDRAM Configuration Register 0 */
     16#define MDREFR		(SMEMC_VIRT + 0x04)  /* SDRAM Refresh Control Register */
     17#define MSC0		(SMEMC_VIRT + 0x08)  /* Static Memory Control Register 0 */
     18#define MSC1		(SMEMC_VIRT + 0x0C)  /* Static Memory Control Register 1 */
     19#define MSC2		(SMEMC_VIRT + 0x10)  /* Static Memory Control Register 2 */
     20#define MECR		(SMEMC_VIRT + 0x14)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
     21#define SXLCR		(SMEMC_VIRT + 0x18)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
     22#define SXCNFG		(SMEMC_VIRT + 0x1C)  /* Synchronous Static Memory Control Register */
     23#define SXMRS		(SMEMC_VIRT + 0x24)  /* MRS value to be written to Synchronous Flash or SMROM */
     24#define MCMEM0		(SMEMC_VIRT + 0x28)  /* Card interface Common Memory Space Socket 0 Timing */
     25#define MCMEM1		(SMEMC_VIRT + 0x2C)  /* Card interface Common Memory Space Socket 1 Timing */
     26#define MCATT0		(SMEMC_VIRT + 0x30)  /* Card interface Attribute Space Socket 0 Timing Configuration */
     27#define MCATT1		(SMEMC_VIRT + 0x34)  /* Card interface Attribute Space Socket 1 Timing Configuration */
     28#define MCIO0		(SMEMC_VIRT + 0x38)  /* Card interface I/O Space Socket 0 Timing Configuration */
     29#define MCIO1		(SMEMC_VIRT + 0x3C)  /* Card interface I/O Space Socket 1 Timing Configuration */
     30#define MDMRS		(SMEMC_VIRT + 0x40)  /* MRS value to be written to SDRAM */
     31#define BOOT_DEF	(SMEMC_VIRT + 0x44)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
     32#define MEMCLKCFG	(SMEMC_VIRT + 0x68)  /* Clock Configuration */
     33#define CSADRCFG0	(SMEMC_VIRT + 0x80)  /* Address Configuration Register for CS0 */
     34#define CSADRCFG1	(SMEMC_VIRT + 0x84)  /* Address Configuration Register for CS1 */
     35#define CSADRCFG2	(SMEMC_VIRT + 0x88)  /* Address Configuration Register for CS2 */
     36#define CSADRCFG3	(SMEMC_VIRT + 0x8C)  /* Address Configuration Register for CS3 */
     37#define CSMSADRCFG	(SMEMC_VIRT + 0xA0)  /* Chip Select Configuration Register */
     38
     39/*
     40 * More handy macros for PCMCIA
     41 *
     42 * Arg is socket number
     43 */
     44#define MCMEM(s)	(SMEMC_VIRT + 0x28 + ((s)<<2))  /* Card interface Common Memory Space Socket s Timing */
     45#define MCATT(s)	(SMEMC_VIRT + 0x30 + ((s)<<2))  /* Card interface Attribute Space Socket s Timing Configuration */
     46#define MCIO(s)		(SMEMC_VIRT + 0x38 + ((s)<<2))  /* Card interface I/O Space Socket s Timing Configuration */
     47
     48/* MECR register defines */
     49#define MECR_NOS	(1 << 0)	/* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
     50#define MECR_CIT	(1 << 1)	/* Card Is There: 0 -> no card, 1 -> card inserted */
     51
     52#define MDCNFG_DE0	(1 << 0)	/* SDRAM Bank 0 Enable */
     53#define MDCNFG_DE1	(1 << 1)	/* SDRAM Bank 1 Enable */
     54#define MDCNFG_DE2	(1 << 16)	/* SDRAM Bank 2 Enable */
     55#define MDCNFG_DE3	(1 << 17)	/* SDRAM Bank 3 Enable */
     56
     57#define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
     58#define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
     59#define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
     60#define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
     61#define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
     62#define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
     63#define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
     64#define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
     65#define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
     66#define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
     67#define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
     68#define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
     69#define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
     70#define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
     71
     72#endif