cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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zeus.h (2221B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  arch/arm/mach-pxa/include/mach/zeus.h
      4 *
      5 *  Author:	David Vrabel
      6 *  Created:	Sept 28, 2005
      7 *  Copyright:	Arcom Control Systems Ltd.
      8 *
      9 *  Maintained by: Marc Zyngier <maz@misterjones.org>
     10 */
     11
     12#ifndef _MACH_ZEUS_H
     13#define _MACH_ZEUS_H
     14
     15#define ZEUS_NR_IRQS		(IRQ_BOARD_START + 48)
     16
     17/* Physical addresses */
     18#define ZEUS_FLASH_PHYS		PXA_CS0_PHYS
     19#define ZEUS_ETH0_PHYS		PXA_CS1_PHYS
     20#define ZEUS_ETH1_PHYS		PXA_CS2_PHYS
     21#define ZEUS_CPLD_PHYS		(PXA_CS4_PHYS+0x2000000)
     22#define ZEUS_SRAM_PHYS		PXA_CS5_PHYS
     23#define ZEUS_PC104IO_PHYS	(0x30000000)
     24
     25#define ZEUS_CPLD_VERSION_PHYS	(ZEUS_CPLD_PHYS + 0x00000000)
     26#define ZEUS_CPLD_ISA_IRQ_PHYS	(ZEUS_CPLD_PHYS + 0x00800000)
     27#define ZEUS_CPLD_CONTROL_PHYS	(ZEUS_CPLD_PHYS + 0x01000000)
     28#define ZEUS_CPLD_EXTWDOG_PHYS	(ZEUS_CPLD_PHYS + 0x01800000)
     29
     30/* GPIOs */
     31#define ZEUS_AC97_GPIO		0
     32#define ZEUS_WAKEUP_GPIO	1
     33#define ZEUS_UARTA_GPIO		9
     34#define ZEUS_UARTB_GPIO		10
     35#define ZEUS_UARTC_GPIO		12
     36#define ZEUS_UARTD_GPIO		11
     37#define ZEUS_ETH0_GPIO		14
     38#define ZEUS_ISA_GPIO		17
     39#define ZEUS_BKLEN_GPIO		19
     40#define ZEUS_USB2_PWREN_GPIO	22
     41#define ZEUS_PTT_GPIO		27
     42#define ZEUS_CF_CD_GPIO         35
     43#define ZEUS_MMC_WP_GPIO        52
     44#define ZEUS_MMC_CD_GPIO        53
     45#define ZEUS_EXTGPIO_GPIO	91
     46#define ZEUS_CF_PWEN_GPIO       97
     47#define ZEUS_CF_RDY_GPIO        99
     48#define ZEUS_LCD_EN_GPIO	101
     49#define ZEUS_ETH1_GPIO		113
     50#define ZEUS_CAN_GPIO		116
     51
     52#define ZEUS_EXT0_GPIO_BASE	128
     53#define ZEUS_EXT1_GPIO_BASE	160
     54#define ZEUS_USER_GPIO_BASE	192
     55
     56#define ZEUS_EXT0_GPIO(x)	(ZEUS_EXT0_GPIO_BASE + (x))
     57#define ZEUS_EXT1_GPIO(x)	(ZEUS_EXT1_GPIO_BASE + (x))
     58#define ZEUS_USER_GPIO(x)	(ZEUS_USER_GPIO_BASE + (x))
     59
     60#define	ZEUS_CAN_SHDN_GPIO	ZEUS_EXT1_GPIO(2)
     61
     62/*
     63 * CPLD registers:
     64 * Only 4 registers, but spread over a 32MB address space.
     65 * Be gentle, and remap that over 32kB...
     66 */
     67
     68#define ZEUS_CPLD		IOMEM(0xf0000000)
     69#define ZEUS_CPLD_VERSION	(ZEUS_CPLD + 0x0000)
     70#define ZEUS_CPLD_ISA_IRQ	(ZEUS_CPLD + 0x1000)
     71#define ZEUS_CPLD_CONTROL	(ZEUS_CPLD + 0x2000)
     72
     73/* CPLD register bits */
     74#define ZEUS_CPLD_CONTROL_CF_RST        0x01
     75
     76#define ZEUS_PC104IO		IOMEM(0xf1000000)
     77
     78#define ZEUS_SRAM_SIZE		(256 * 1024)
     79
     80#endif
     81
     82