bast.h (6050B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2003-2004 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * BAST - CPLD control constants 7 * BAST - IRQ Number definitions 8 * BAST - Memory map definitions 9 */ 10 11#ifndef __MACH_S3C24XX_BAST_H 12#define __MACH_S3C24XX_BAST_H __FILE__ 13 14/* CTRL1 - Audio LR routing */ 15 16#define BAST_CPLD_CTRL1_LRCOFF (0x00) 17#define BAST_CPLD_CTRL1_LRCADC (0x01) 18#define BAST_CPLD_CTRL1_LRCDAC (0x02) 19#define BAST_CPLD_CTRL1_LRCARM (0x03) 20#define BAST_CPLD_CTRL1_LRMASK (0x03) 21 22/* CTRL2 - NAND WP control, IDE Reset assert/check */ 23 24#define BAST_CPLD_CTRL2_WNAND (0x04) 25#define BAST_CPLD_CTLR2_IDERST (0x08) 26 27/* CTRL3 - rom write control, CPLD identity */ 28 29#define BAST_CPLD_CTRL3_IDMASK (0x0e) 30#define BAST_CPLD_CTRL3_ROMWEN (0x01) 31 32/* CTRL4 - 8bit LCD interface control/status */ 33 34#define BAST_CPLD_CTRL4_LLAT (0x01) 35#define BAST_CPLD_CTRL4_LCDRW (0x02) 36#define BAST_CPLD_CTRL4_LCDCMD (0x04) 37#define BAST_CPLD_CTRL4_LCDE2 (0x01) 38 39/* CTRL5 - DMA routing */ 40 41#define BAST_CPLD_DMA0_PRIIDE (0) 42#define BAST_CPLD_DMA0_SECIDE (1) 43#define BAST_CPLD_DMA0_ISA15 (2) 44#define BAST_CPLD_DMA0_ISA36 (3) 45 46#define BAST_CPLD_DMA1_PRIIDE (0 << 2) 47#define BAST_CPLD_DMA1_SECIDE (1 << 2) 48#define BAST_CPLD_DMA1_ISA15 (2 << 2) 49#define BAST_CPLD_DMA1_ISA36 (3 << 2) 50 51/* irq numbers to onboard peripherals */ 52 53#define BAST_IRQ_USBOC IRQ_EINT18 54#define BAST_IRQ_IDE0 IRQ_EINT16 55#define BAST_IRQ_IDE1 IRQ_EINT17 56#define BAST_IRQ_PCSERIAL1 IRQ_EINT15 57#define BAST_IRQ_PCSERIAL2 IRQ_EINT14 58#define BAST_IRQ_PCPARALLEL IRQ_EINT13 59#define BAST_IRQ_ASIX IRQ_EINT11 60#define BAST_IRQ_DM9000 IRQ_EINT10 61#define BAST_IRQ_ISA IRQ_EINT9 62#define BAST_IRQ_SMALERT IRQ_EINT8 63 64/* map */ 65 66/* 67 * ok, we've used up to 0x13000000, now we need to find space for the 68 * peripherals that live in the nGCS[x] areas, which are quite numerous 69 * in their space. We also have the board's CPLD to find register space 70 * for. 71 */ 72 73#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) 74 75/* we put the CPLD registers next, to get them out of the way */ 76 77#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) 78#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) 79 80#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) 81#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) 82 83#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) 84#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) 85 86#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) 87#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) 88 89/* next, we have the PC104 ISA interrupt registers */ 90 91#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) 92#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) 93 94#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) 95#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) 96 97#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) 98#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) 99 100#define BAST_PA_LCD_RCMD1 (0x8800000) 101#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) 102 103#define BAST_PA_LCD_WCMD1 (0x8000000) 104#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) 105 106#define BAST_PA_LCD_RDATA1 (0x9800000) 107#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) 108 109#define BAST_PA_LCD_WDATA1 (0x9000000) 110#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) 111 112#define BAST_PA_LCD_RCMD2 (0xA800000) 113#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) 114 115#define BAST_PA_LCD_WCMD2 (0xA000000) 116#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) 117 118#define BAST_PA_LCD_RDATA2 (0xB800000) 119#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) 120 121#define BAST_PA_LCD_WDATA2 (0xB000000) 122#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) 123 124 125/* 126 * 0xE0000000 contains the IO space that is split by speed and 127 * whether the access is for 8 or 16bit IO... this ensures that 128 * the correct access is made 129 * 130 * 0x10000000 of space, partitioned as so: 131 * 132 * 0x00000000 to 0x04000000 8bit, slow 133 * 0x04000000 to 0x08000000 16bit, slow 134 * 0x08000000 to 0x0C000000 16bit, net 135 * 0x0C000000 to 0x10000000 16bit, fast 136 * 137 * each of these spaces has the following in: 138 * 139 * 0x00000000 to 0x01000000 16MB ISA IO space 140 * 0x01000000 to 0x02000000 16MB ISA memory space 141 * 0x02000000 to 0x02100000 1MB IDE primary channel 142 * 0x02100000 to 0x02200000 1MB IDE primary channel aux 143 * 0x02200000 to 0x02400000 1MB IDE secondary channel 144 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux 145 * 0x02400000 to 0x02500000 1MB ASIX ethernet controller 146 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller 147 * 0x02600000 to 0x02700000 1MB PC SuperIO controller 148 * 149 * the phyiscal layout of the zones are: 150 * nGCS2 - 8bit, slow 151 * nGCS3 - 16bit, slow 152 * nGCS4 - 16bit, net 153 * nGCS5 - 16bit, fast 154 */ 155 156#define BAST_VA_MULTISPACE (0xE0000000) 157 158#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) 159#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) 160#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) 161#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) 162#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) 163#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) 164#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) 165#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) 166#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) 167 168#define BAST_VAM_CS2 (0x00000000) 169#define BAST_VAM_CS3 (0x04000000) 170#define BAST_VAM_CS4 (0x08000000) 171#define BAST_VAM_CS5 (0x0C000000) 172 173/* physical offset addresses for the peripherals */ 174 175#define BAST_PA_ISAIO (0x00000000) 176#define BAST_PA_ASIXNET (0x01000000) 177#define BAST_PA_SUPERIO (0x01800000) 178#define BAST_PA_IDEPRI (0x02000000) 179#define BAST_PA_IDEPRIAUX (0x02800000) 180#define BAST_PA_IDESEC (0x03000000) 181#define BAST_PA_IDESECAUX (0x03800000) 182#define BAST_PA_ISAMEM (0x04000000) 183#define BAST_PA_DM9000 (0x05000000) 184 185/* some configurations for the peripherals */ 186 187#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) 188 189#define BAST_ASIXNET_CS BAST_VAM_CS5 190#define BAST_DM9000_CS BAST_VAM_CS4 191 192#define BAST_IDE_CS S3C2410_CS5 193 194#endif /* __MACH_S3C24XX_BAST_H */