cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mach-amlm5900.c (5833B)


      1// SPDX-License-Identifier: GPL-2.0+
      2//
      3// Copyright (c) 2006 American Microsystems Limited
      4//	David Anders <danders@amltd.com>
      5//
      6// @History:
      7// derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
      8// Ben Dooks <ben@simtec.co.uk>
      9
     10#include <linux/kernel.h>
     11#include <linux/types.h>
     12#include <linux/interrupt.h>
     13#include <linux/list.h>
     14#include <linux/timer.h>
     15#include <linux/init.h>
     16#include <linux/gpio/machine.h>
     17#include <linux/gpio.h>
     18#include <linux/device.h>
     19#include <linux/platform_device.h>
     20#include <linux/proc_fs.h>
     21#include <linux/serial_core.h>
     22#include <linux/serial_s3c.h>
     23#include <linux/io.h>
     24
     25#include <asm/mach/arch.h>
     26#include <asm/mach/map.h>
     27#include <asm/mach/irq.h>
     28#include <asm/mach/flash.h>
     29
     30#include <asm/irq.h>
     31#include <asm/mach-types.h>
     32#include <linux/platform_data/fb-s3c2410.h>
     33
     34#include "regs-gpio.h"
     35#include "gpio-samsung.h"
     36
     37#include <linux/platform_data/i2c-s3c2410.h>
     38#include "devs.h"
     39#include "cpu.h"
     40#include "gpio-cfg.h"
     41
     42#include <linux/mtd/mtd.h>
     43#include <linux/mtd/partitions.h>
     44#include <linux/mtd/map.h>
     45#include <linux/mtd/physmap.h>
     46
     47#include "s3c24xx.h"
     48
     49static struct resource amlm5900_nor_resource =
     50			DEFINE_RES_MEM(0x00000000, SZ_16M);
     51
     52static struct mtd_partition amlm5900_mtd_partitions[] = {
     53	{
     54		.name		= "System",
     55		.size		= 0x240000,
     56		.offset		= 0,
     57		.mask_flags 	= MTD_WRITEABLE,  /* force read-only */
     58	}, {
     59		.name		= "Kernel",
     60		.size		= 0x100000,
     61		.offset		= MTDPART_OFS_APPEND,
     62	}, {
     63		.name		= "Ramdisk",
     64		.size		= 0x300000,
     65		.offset		= MTDPART_OFS_APPEND,
     66	}, {
     67		.name		= "JFFS2",
     68		.size		= 0x9A0000,
     69		.offset		= MTDPART_OFS_APPEND,
     70	}, {
     71		.name		= "Settings",
     72		.size		= MTDPART_SIZ_FULL,
     73		.offset		= MTDPART_OFS_APPEND,
     74	}
     75};
     76
     77static struct physmap_flash_data amlm5900_flash_data = {
     78	.width		= 2,
     79	.parts		= amlm5900_mtd_partitions,
     80	.nr_parts	= ARRAY_SIZE(amlm5900_mtd_partitions),
     81};
     82
     83static struct platform_device amlm5900_device_nor = {
     84	.name		= "physmap-flash",
     85	.id		= 0,
     86	.dev = {
     87			.platform_data = &amlm5900_flash_data,
     88		},
     89	.num_resources	= 1,
     90	.resource	= &amlm5900_nor_resource,
     91};
     92
     93static struct map_desc amlm5900_iodesc[] __initdata = {
     94};
     95
     96#define UCON S3C2410_UCON_DEFAULT
     97#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
     98#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
     99
    100static struct s3c2410_uartcfg amlm5900_uartcfgs[] = {
    101	[0] = {
    102		.hwport	     = 0,
    103		.flags	     = 0,
    104		.ucon	     = UCON,
    105		.ulcon	     = ULCON,
    106		.ufcon	     = UFCON,
    107	},
    108	[1] = {
    109		.hwport	     = 1,
    110		.flags	     = 0,
    111		.ucon	     = UCON,
    112		.ulcon	     = ULCON,
    113		.ufcon	     = UFCON,
    114	},
    115	[2] = {
    116		.hwport	     = 2,
    117		.flags	     = 0,
    118		.ucon	     = UCON,
    119		.ulcon	     = ULCON,
    120		.ufcon	     = UFCON,
    121	}
    122};
    123
    124static struct gpiod_lookup_table amlm5900_mmc_gpio_table = {
    125	.dev_id = "s3c2410-sdi",
    126	.table = {
    127		/* bus pins */
    128		GPIO_LOOKUP_IDX("GPIOE",  5, "bus", 0, GPIO_ACTIVE_HIGH),
    129		GPIO_LOOKUP_IDX("GPIOE",  6, "bus", 1, GPIO_ACTIVE_HIGH),
    130		GPIO_LOOKUP_IDX("GPIOE",  7, "bus", 2, GPIO_ACTIVE_HIGH),
    131		GPIO_LOOKUP_IDX("GPIOE",  8, "bus", 3, GPIO_ACTIVE_HIGH),
    132		GPIO_LOOKUP_IDX("GPIOE",  9, "bus", 4, GPIO_ACTIVE_HIGH),
    133		GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
    134		{ },
    135	},
    136};
    137
    138static struct platform_device *amlm5900_devices[] __initdata = {
    139#ifdef CONFIG_FB_S3C2410
    140	&s3c_device_lcd,
    141#endif
    142	&s3c_device_adc,
    143	&s3c_device_wdt,
    144	&s3c_device_i2c0,
    145	&s3c_device_ohci,
    146 	&s3c_device_rtc,
    147	&s3c_device_usbgadget,
    148        &s3c_device_sdi,
    149	&amlm5900_device_nor,
    150};
    151
    152static void __init amlm5900_map_io(void)
    153{
    154	s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
    155	s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
    156	s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
    157}
    158
    159static void __init amlm5900_init_time(void)
    160{
    161	s3c2410_init_clocks(12000000);
    162	s3c24xx_timer_init();
    163}
    164
    165#ifdef CONFIG_FB_S3C2410
    166static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
    167	.width		= 160,
    168	.height		= 160,
    169
    170	.type		= S3C2410_LCDCON1_STN4,
    171
    172	.pixclock	= 680000, /* HCLK = 100MHz */
    173	.xres		= 160,
    174	.yres		= 160,
    175	.bpp		= 4,
    176	.left_margin	= 1 << (4 + 3),
    177	.right_margin	= 8 << 3,
    178	.hsync_len	= 48,
    179	.upper_margin	= 0,
    180	.lower_margin	= 0,
    181
    182	.lcdcon5	= 0x00000001,
    183};
    184
    185static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = {
    186
    187	.displays = &amlm5900_lcd_info,
    188	.num_displays = 1,
    189	.default_display = 0,
    190
    191	.gpccon =	0xaaaaaaaa,
    192	.gpccon_mask =	0xffffffff,
    193	.gpccon_reg =	S3C2410_GPCCON,
    194	.gpcup =	0x0000ffff,
    195	.gpcup_mask =	0xffffffff,
    196	.gpcup_reg =	S3C2410_GPCUP,
    197
    198	.gpdcon =	0xaaaaaaaa,
    199	.gpdcon_mask =	0xffffffff,
    200	.gpdcon_reg =	S3C2410_GPDCON,
    201	.gpdup =	0x0000ffff,
    202	.gpdup_mask =	0xffffffff,
    203	.gpdup_reg =	S3C2410_GPDUP,
    204};
    205#endif
    206
    207static irqreturn_t
    208amlm5900_wake_interrupt(int irq, void *ignored)
    209{
    210	return IRQ_HANDLED;
    211}
    212
    213static void amlm5900_init_pm(void)
    214{
    215	int ret = 0;
    216
    217	ret = request_irq(IRQ_EINT9, &amlm5900_wake_interrupt,
    218				IRQF_TRIGGER_RISING | IRQF_SHARED,
    219				"amlm5900_wakeup", &amlm5900_wake_interrupt);
    220	if (ret != 0) {
    221		printk(KERN_ERR "AML-M5900: no wakeup irq, %d?\n", ret);
    222	} else {
    223		enable_irq_wake(IRQ_EINT9);
    224		/* configure the suspend/resume status pin */
    225		s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
    226		s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP);
    227	}
    228}
    229static void __init amlm5900_init(void)
    230{
    231	amlm5900_init_pm();
    232#ifdef CONFIG_FB_S3C2410
    233	s3c24xx_fb_set_platdata(&amlm5900_fb_info);
    234#endif
    235	s3c_i2c0_set_platdata(NULL);
    236	gpiod_add_lookup_table(&amlm5900_mmc_gpio_table);
    237	platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
    238}
    239
    240MACHINE_START(AML_M5900, "AML_M5900")
    241	.atag_offset	= 0x100,
    242	.nr_irqs	= NR_IRQS_S3C2410,
    243	.map_io		= amlm5900_map_io,
    244	.nr_irqs	= NR_IRQS_S3C2410,
    245	.init_irq	= s3c2410_init_irq,
    246	.init_machine	= amlm5900_init,
    247	.init_time	= amlm5900_init_time,
    248MACHINE_END