cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mach-at2440evb.c (5831B)


      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
      4//      Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
      5//      and modifications by SBZ <sbz@spgui.org> and
      6//      Weibing <http://weibing.blogbus.com>
      7//
      8// For product information, visit http://www.arm.com/
      9
     10#include <linux/kernel.h>
     11#include <linux/types.h>
     12#include <linux/gpio/machine.h>
     13#include <linux/interrupt.h>
     14#include <linux/list.h>
     15#include <linux/timer.h>
     16#include <linux/init.h>
     17#include <linux/io.h>
     18#include <linux/serial_core.h>
     19#include <linux/serial_s3c.h>
     20#include <linux/dm9000.h>
     21#include <linux/platform_device.h>
     22
     23#include <asm/mach/arch.h>
     24#include <asm/mach/map.h>
     25#include <asm/mach/irq.h>
     26
     27#include <linux/platform_data/fb-s3c2410.h>
     28#include <asm/irq.h>
     29#include <asm/mach-types.h>
     30
     31#include "regs-gpio.h"
     32#include "gpio-samsung.h"
     33#include <linux/platform_data/mtd-nand-s3c2410.h>
     34#include <linux/platform_data/i2c-s3c2410.h>
     35
     36#include <linux/mtd/mtd.h>
     37#include <linux/mtd/rawnand.h>
     38#include <linux/mtd/nand-ecc-sw-hamming.h>
     39#include <linux/mtd/partitions.h>
     40
     41#include "devs.h"
     42#include "cpu.h"
     43#include <linux/platform_data/mmc-s3cmci.h>
     44
     45#include "s3c24xx.h"
     46
     47static struct map_desc at2440evb_iodesc[] __initdata = {
     48	/* Nothing here */
     49};
     50
     51#define UCON S3C2410_UCON_DEFAULT
     52#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
     53#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
     54
     55static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
     56	[0] = {
     57		.hwport	     = 0,
     58		.flags	     = 0,
     59		.ucon	     = UCON,
     60		.ulcon	     = ULCON,
     61		.ufcon	     = UFCON,
     62		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
     63	},
     64	[1] = {
     65		.hwport	     = 1,
     66		.flags	     = 0,
     67		.ucon	     = UCON,
     68		.ulcon	     = ULCON,
     69		.ufcon	     = UFCON,
     70		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
     71	},
     72};
     73
     74/* NAND Flash on AT2440EVB board */
     75
     76static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
     77	[0] = {
     78		.name	= "Boot Agent",
     79		.size	= SZ_256K,
     80		.offset	= 0,
     81	},
     82	[1] = {
     83		.name	= "Kernel",
     84		.size	= SZ_2M,
     85		.offset	= SZ_256K,
     86	},
     87	[2] = {
     88		.name	= "Root",
     89		.offset	= SZ_256K + SZ_2M,
     90		.size	= MTDPART_SIZ_FULL,
     91	},
     92};
     93
     94static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
     95	[0] = {
     96		.name		= "nand",
     97		.nr_chips	= 1,
     98		.nr_partitions	= ARRAY_SIZE(at2440evb_default_nand_part),
     99		.partitions	= at2440evb_default_nand_part,
    100	},
    101};
    102
    103static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
    104	.tacls		= 25,
    105	.twrph0		= 55,
    106	.twrph1		= 40,
    107	.nr_sets	= ARRAY_SIZE(at2440evb_nand_sets),
    108	.sets		= at2440evb_nand_sets,
    109	.engine_type	= NAND_ECC_ENGINE_TYPE_SOFT,
    110};
    111
    112/* DM9000AEP 10/100 ethernet controller */
    113
    114static struct resource at2440evb_dm9k_resource[] = {
    115	[0] = DEFINE_RES_MEM(S3C2410_CS3, 4),
    116	[1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4),
    117	[2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
    118					| IORESOURCE_IRQ_HIGHEDGE),
    119};
    120
    121static struct dm9000_plat_data at2440evb_dm9k_pdata = {
    122	.flags		= (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
    123};
    124
    125static struct platform_device at2440evb_device_eth = {
    126	.name		= "dm9000",
    127	.id		= -1,
    128	.num_resources	= ARRAY_SIZE(at2440evb_dm9k_resource),
    129	.resource	= at2440evb_dm9k_resource,
    130	.dev		= {
    131		.platform_data	= &at2440evb_dm9k_pdata,
    132	},
    133};
    134
    135static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
    136	.set_power	= s3c24xx_mci_def_set_power,
    137};
    138
    139static struct gpiod_lookup_table at2440evb_mci_gpio_table = {
    140	.dev_id = "s3c2410-sdi",
    141	.table = {
    142		/* Card detect S3C2410_GPG(10) */
    143		GPIO_LOOKUP("GPIOG", 10, "cd", GPIO_ACTIVE_LOW),
    144		/* bus pins */
    145		GPIO_LOOKUP_IDX("GPIOE",  5, "bus", 0, GPIO_ACTIVE_HIGH),
    146		GPIO_LOOKUP_IDX("GPIOE",  6, "bus", 1, GPIO_ACTIVE_HIGH),
    147		GPIO_LOOKUP_IDX("GPIOE",  7, "bus", 2, GPIO_ACTIVE_HIGH),
    148		GPIO_LOOKUP_IDX("GPIOE",  8, "bus", 3, GPIO_ACTIVE_HIGH),
    149		GPIO_LOOKUP_IDX("GPIOE",  9, "bus", 4, GPIO_ACTIVE_HIGH),
    150		GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
    151		{ },
    152	},
    153};
    154
    155
    156/* 7" LCD panel */
    157
    158static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
    159
    160	.lcdcon5	= S3C2410_LCDCON5_FRM565 |
    161			  S3C2410_LCDCON5_INVVLINE |
    162			  S3C2410_LCDCON5_INVVFRAME |
    163			  S3C2410_LCDCON5_PWREN |
    164			  S3C2410_LCDCON5_HWSWP,
    165
    166	.type		= S3C2410_LCDCON1_TFT,
    167
    168	.width		= 800,
    169	.height		= 480,
    170
    171	.pixclock	= 33333, /* HCLK 60 MHz, divisor 2 */
    172	.xres		= 800,
    173	.yres		= 480,
    174	.bpp		= 16,
    175	.left_margin	= 88,
    176	.right_margin	= 40,
    177	.hsync_len	= 128,
    178	.upper_margin	= 32,
    179	.lower_margin	= 11,
    180	.vsync_len	= 2,
    181};
    182
    183static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
    184	.displays	= &at2440evb_lcd_cfg,
    185	.num_displays	= 1,
    186	.default_display = 0,
    187};
    188
    189static struct platform_device *at2440evb_devices[] __initdata = {
    190	&s3c_device_ohci,
    191	&s3c_device_wdt,
    192	&s3c_device_adc,
    193	&s3c_device_i2c0,
    194	&s3c_device_rtc,
    195	&s3c_device_nand,
    196	&s3c_device_sdi,
    197	&s3c_device_lcd,
    198	&at2440evb_device_eth,
    199};
    200
    201static void __init at2440evb_map_io(void)
    202{
    203	s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
    204	s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
    205	s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
    206}
    207
    208static void __init at2440evb_init_time(void)
    209{
    210	s3c2440_init_clocks(16934400);
    211	s3c24xx_timer_init();
    212}
    213
    214static void __init at2440evb_init(void)
    215{
    216	s3c24xx_fb_set_platdata(&at2440evb_fb_info);
    217	gpiod_add_lookup_table(&at2440evb_mci_gpio_table);
    218	s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
    219	s3c_nand_set_platdata(&at2440evb_nand_info);
    220	s3c_i2c0_set_platdata(NULL);
    221
    222	platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
    223}
    224
    225
    226MACHINE_START(AT2440EVB, "AT2440EVB")
    227	.atag_offset	= 0x100,
    228	.nr_irqs	= NR_IRQS_S3C2440,
    229	.map_io		= at2440evb_map_io,
    230	.init_machine	= at2440evb_init,
    231	.init_irq	= s3c2440_init_irq,
    232	.init_time	= at2440evb_init_time,
    233MACHINE_END