cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mach-otom.c (2923B)

      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// Copyright (c) 2004 Nex Vision
      4//   Guillaume GOURAT <guillaume.gourat@nexvision.fr>
      5
      6#include <linux/kernel.h>
      7#include <linux/types.h>
      8#include <linux/interrupt.h>
      9#include <linux/list.h>
     10#include <linux/timer.h>
     11#include <linux/init.h>
     12#include <linux/serial_core.h>
     13#include <linux/serial_s3c.h>
     14#include <linux/platform_device.h>
     15#include <linux/io.h>
     16
     17#include <linux/platform_data/i2c-s3c2410.h>
     18
     19#include <asm/irq.h>
     20#include <asm/mach-types.h>
     21#include <asm/mach/arch.h>
     22#include <asm/mach/map.h>
     23#include <asm/mach/irq.h>
     24
     25#include "gpio-samsung.h"
     26#include "gpio-cfg.h"
     27
     28#include "cpu.h"
     29#include "devs.h"
     30
     31#include "s3c24xx.h"
     32#include "otom.h"
     33
     34static struct map_desc otom11_iodesc[] __initdata = {
     35  /* Device area */
     36	{ (u32)OTOM_VA_CS8900A_BASE, OTOM_PA_CS8900A_BASE, SZ_16M, MT_DEVICE },
     37};
     38
     39#define UCON S3C2410_UCON_DEFAULT
     40#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
     41#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
     42
     43static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = {
     44	[0] = {
     45		.hwport	     = 0,
     46		.flags	     = 0,
     47		.ucon	     = UCON,
     48		.ulcon	     = ULCON,
     49		.ufcon	     = UFCON,
     50	},
     51	[1] = {
     52		.hwport	     = 1,
     53		.flags	     = 0,
     54		.ucon	     = UCON,
     55		.ulcon	     = ULCON,
     56		.ufcon	     = UFCON,
     57	},
     58	/* port 2 is not actually used */
     59	[2] = {
     60		.hwport	     = 2,
     61		.flags	     = 0,
     62		.ucon	     = UCON,
     63		.ulcon	     = ULCON,
     64		.ufcon	     = UFCON,
     65	}
     66};
     67
     68/* NOR Flash on NexVision OTOM board */
     69
     70static struct resource otom_nor_resource[] = {
     71	[0] = DEFINE_RES_MEM(S3C2410_CS0, SZ_4M),
     72};
     73
     74static struct platform_device otom_device_nor = {
     75	.name		= "mtd-flash",
     76	.id		= -1,
     77	.num_resources	= ARRAY_SIZE(otom_nor_resource),
     78	.resource	= otom_nor_resource,
     79};
     80
     81/* Standard OTOM devices */
     82
     83static struct platform_device *otom11_devices[] __initdata = {
     84	&s3c_device_ohci,
     85	&s3c_device_lcd,
     86	&s3c_device_wdt,
     87	&s3c_device_i2c0,
     88	&s3c_device_iis,
     89 	&s3c_device_rtc,
     90	&otom_device_nor,
     91};
     92
     93static void __init otom11_map_io(void)
     94{
     95	s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
     96	s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
     97	s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
     98}
     99
    100static void __init otom11_init_time(void)
    101{
    102	s3c2410_init_clocks(12000000);
    103	s3c24xx_timer_init();
    104}
    105
    106static void __init otom11_init(void)
    107{
    108	s3c_i2c0_set_platdata(NULL);
    109
    110	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
    111	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
    112			      S3C_GPIO_PULL_NONE);
    113	platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
    114}
    115
    116MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
    117	/* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
    118	.atag_offset	= 0x100,
    119	.nr_irqs	= NR_IRQS_S3C2410,
    120	.map_io		= otom11_map_io,
    121	.init_machine	= otom11_init,
    122	.init_irq	= s3c2410_init_irq,
    123	.init_time	= otom11_init_time,
    124MACHINE_END