cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pll-s3c2440-12000000.c (4041B)

      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// Copyright (c) 2006-2007 Simtec Electronics
      4//	http://armlinux.simtec.co.uk/
      5//	Ben Dooks <ben@simtec.co.uk>
      6//	Vincent Sanders <vince@arm.linux.org.uk>
      7//
      8// S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
      9
     10#include <linux/types.h>
     11#include <linux/kernel.h>
     12#include <linux/device.h>
     13#include <linux/clk.h>
     14#include <linux/err.h>
     15
     16#include <linux/soc/samsung/s3c-cpufreq-core.h>
     17#include <linux/soc/samsung/s3c-pm.h>
     18
     19/* This array should be sorted in ascending order of the frequencies */
     20static struct cpufreq_frequency_table s3c2440_plls_12[] = {
     21	{ .frequency = 75000000,	.driver_data = PLLVAL(0x75, 3, 3),  }, 	/* FVco 600.000000 */
     22	{ .frequency = 80000000,	.driver_data = PLLVAL(0x98, 4, 3),  }, 	/* FVco 640.000000 */
     23	{ .frequency = 90000000,	.driver_data = PLLVAL(0x70, 2, 3),  }, 	/* FVco 720.000000 */
     24	{ .frequency = 100000000,	.driver_data = PLLVAL(0x5c, 1, 3),  }, 	/* FVco 800.000000 */
     25	{ .frequency = 110000000,	.driver_data = PLLVAL(0x66, 1, 3),  }, 	/* FVco 880.000000 */
     26	{ .frequency = 120000000,	.driver_data = PLLVAL(0x70, 1, 3),  }, 	/* FVco 960.000000 */
     27	{ .frequency = 150000000,	.driver_data = PLLVAL(0x75, 3, 2),  }, 	/* FVco 600.000000 */
     28	{ .frequency = 160000000,	.driver_data = PLLVAL(0x98, 4, 2),  }, 	/* FVco 640.000000 */
     29	{ .frequency = 170000000,	.driver_data = PLLVAL(0x4d, 1, 2),  }, 	/* FVco 680.000000 */
     30	{ .frequency = 180000000,	.driver_data = PLLVAL(0x70, 2, 2),  }, 	/* FVco 720.000000 */
     31	{ .frequency = 190000000,	.driver_data = PLLVAL(0x57, 1, 2),  }, 	/* FVco 760.000000 */
     32	{ .frequency = 200000000,	.driver_data = PLLVAL(0x5c, 1, 2),  }, 	/* FVco 800.000000 */
     33	{ .frequency = 210000000,	.driver_data = PLLVAL(0x84, 2, 2),  }, 	/* FVco 840.000000 */
     34	{ .frequency = 220000000,	.driver_data = PLLVAL(0x66, 1, 2),  }, 	/* FVco 880.000000 */
     35	{ .frequency = 230000000,	.driver_data = PLLVAL(0x6b, 1, 2),  }, 	/* FVco 920.000000 */
     36	{ .frequency = 240000000,	.driver_data = PLLVAL(0x70, 1, 2),  }, 	/* FVco 960.000000 */
     37	{ .frequency = 300000000,	.driver_data = PLLVAL(0x75, 3, 1),  }, 	/* FVco 600.000000 */
     38	{ .frequency = 310000000,	.driver_data = PLLVAL(0x93, 4, 1),  }, 	/* FVco 620.000000 */
     39	{ .frequency = 320000000,	.driver_data = PLLVAL(0x98, 4, 1),  }, 	/* FVco 640.000000 */
     40	{ .frequency = 330000000,	.driver_data = PLLVAL(0x66, 2, 1),  }, 	/* FVco 660.000000 */
     41	{ .frequency = 340000000,	.driver_data = PLLVAL(0x4d, 1, 1),  }, 	/* FVco 680.000000 */
     42	{ .frequency = 350000000,	.driver_data = PLLVAL(0xa7, 4, 1),  }, 	/* FVco 700.000000 */
     43	{ .frequency = 360000000,	.driver_data = PLLVAL(0x70, 2, 1),  }, 	/* FVco 720.000000 */
     44	{ .frequency = 370000000,	.driver_data = PLLVAL(0xb1, 4, 1),  }, 	/* FVco 740.000000 */
     45	{ .frequency = 380000000,	.driver_data = PLLVAL(0x57, 1, 1),  }, 	/* FVco 760.000000 */
     46	{ .frequency = 390000000,	.driver_data = PLLVAL(0x7a, 2, 1),  }, 	/* FVco 780.000000 */
     47	{ .frequency = 400000000,	.driver_data = PLLVAL(0x5c, 1, 1),  }, 	/* FVco 800.000000 */
     48};
     49
     50static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
     51{
     52	struct clk *xtal_clk;
     53	unsigned long xtal;
     54
     55	xtal_clk = clk_get(NULL, "xtal");
     56	if (IS_ERR(xtal_clk))
     57		return PTR_ERR(xtal_clk);
     58
     59	xtal = clk_get_rate(xtal_clk);
     60	clk_put(xtal_clk);
     61
     62	if (xtal == 12000000) {
     63		printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
     64		return s3c_plltab_register(s3c2440_plls_12,
     65					   ARRAY_SIZE(s3c2440_plls_12));
     66	}
     67
     68	return 0;
     69}
     70
     71static struct subsys_interface s3c2440_plls12_interface = {
     72	.name		= "s3c2440_plls12",
     73	.subsys		= &s3c2440_subsys,
     74	.add_dev	= s3c2440_plls12_add,
     75};
     76
     77static int __init s3c2440_pll_12mhz(void)
     78{
     79	return subsys_interface_register(&s3c2440_plls12_interface);
     80
     81}
     82arch_initcall(s3c2440_pll_12mhz);
     83
     84static struct subsys_interface s3c2442_plls12_interface = {
     85	.name		= "s3c2442_plls12",
     86	.subsys		= &s3c2442_subsys,
     87	.add_dev	= s3c2440_plls12_add,
     88};
     89
     90static int __init s3c2442_pll_12mhz(void)
     91{
     92	return subsys_interface_register(&s3c2442_plls12_interface);
     93
     94}
     95arch_initcall(s3c2442_pll_12mhz);