regs-gpio-s3c24xx.h (19022B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * S3C2410 GPIO register definitions 7 */ 8 9 10#ifndef __ASM_ARCH_REGS_GPIO_H 11#define __ASM_ARCH_REGS_GPIO_H 12 13#include "map-s3c.h" 14 15#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) 16 17/* general configuration options */ 18 19#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 20#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ 21#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) 22#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ 23#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ 24#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ 25 26/* register address for the GPIO registers. 27 * S3C24XX_GPIOREG2 is for the second set of registers in the 28 * GPIO which move between s3c2410 and s3c2412 type systems */ 29 30#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) 31#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) 32 33 34/* configure GPIO ports A..G */ 35 36/* port A - S3C2410: 22bits, zero in bit X makes pin X output 37 * 1 makes port special function, this is default 38*/ 39#define S3C2410_GPACON S3C2410_GPIOREG(0x00) 40#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) 41 42#define S3C2410_GPA0_ADDR0 (1<<0) 43#define S3C2410_GPA1_ADDR16 (1<<1) 44#define S3C2410_GPA2_ADDR17 (1<<2) 45#define S3C2410_GPA3_ADDR18 (1<<3) 46#define S3C2410_GPA4_ADDR19 (1<<4) 47#define S3C2410_GPA5_ADDR20 (1<<5) 48#define S3C2410_GPA6_ADDR21 (1<<6) 49#define S3C2410_GPA7_ADDR22 (1<<7) 50#define S3C2410_GPA8_ADDR23 (1<<8) 51#define S3C2410_GPA9_ADDR24 (1<<9) 52#define S3C2410_GPA10_ADDR25 (1<<10) 53#define S3C2410_GPA11_ADDR26 (1<<11) 54#define S3C2410_GPA12_nGCS1 (1<<12) 55#define S3C2410_GPA13_nGCS2 (1<<13) 56#define S3C2410_GPA14_nGCS3 (1<<14) 57#define S3C2410_GPA15_nGCS4 (1<<15) 58#define S3C2410_GPA16_nGCS5 (1<<16) 59#define S3C2410_GPA17_CLE (1<<17) 60#define S3C2410_GPA18_ALE (1<<18) 61#define S3C2410_GPA19_nFWE (1<<19) 62#define S3C2410_GPA20_nFRE (1<<20) 63#define S3C2410_GPA21_nRSTOUT (1<<21) 64#define S3C2410_GPA22_nFCE (1<<22) 65 66/* 0x08 and 0x0c are reserved on S3C2410 */ 67 68/* S3C2410: 69 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. 70 * 00 = input, 01 = output, 10=special function, 11=reserved 71 72 * bit 0,1 = pin 0, 2,3= pin 1... 73 * 74 * CPBUP = pull up resistor control, 1=disabled, 0=enabled 75*/ 76 77#define S3C2410_GPBCON S3C2410_GPIOREG(0x10) 78#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) 79#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) 80 81/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ 82 83#define S3C2410_GPB0_TOUT0 (0x02 << 0) 84 85#define S3C2410_GPB1_TOUT1 (0x02 << 2) 86 87#define S3C2410_GPB2_TOUT2 (0x02 << 4) 88 89#define S3C2410_GPB3_TOUT3 (0x02 << 6) 90 91#define S3C2410_GPB4_TCLK0 (0x02 << 8) 92#define S3C2410_GPB4_MASK (0x03 << 8) 93 94#define S3C2410_GPB5_nXBACK (0x02 << 10) 95#define S3C2443_GPB5_XBACK (0x03 << 10) 96 97#define S3C2410_GPB6_nXBREQ (0x02 << 12) 98#define S3C2443_GPB6_XBREQ (0x03 << 12) 99 100#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 101#define S3C2443_GPB7_XDACK1 (0x03 << 14) 102 103#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 104 105#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 106#define S3C2443_GPB9_XDACK0 (0x03 << 18) 107 108#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 109#define S3C2443_GPB10_XDREQ0 (0x03 << 20) 110 111#define S3C2410_GPB_PUPDIS(x) (1<<(x)) 112 113/* Port C consits of 16 GPIO/Special function 114 * 115 * almost identical setup to port b, but the special functions are mostly 116 * to do with the video system's sync/etc. 117*/ 118 119#define S3C2410_GPCCON S3C2410_GPIOREG(0x20) 120#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) 121#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) 122#define S3C2410_GPC0_LEND (0x02 << 0) 123#define S3C2410_GPC1_VCLK (0x02 << 2) 124#define S3C2410_GPC2_VLINE (0x02 << 4) 125#define S3C2410_GPC3_VFRAME (0x02 << 6) 126#define S3C2410_GPC4_VM (0x02 << 8) 127#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 128#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 129#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 130#define S3C2410_GPC8_VD0 (0x02 << 16) 131#define S3C2410_GPC9_VD1 (0x02 << 18) 132#define S3C2410_GPC10_VD2 (0x02 << 20) 133#define S3C2410_GPC11_VD3 (0x02 << 22) 134#define S3C2410_GPC12_VD4 (0x02 << 24) 135#define S3C2410_GPC13_VD5 (0x02 << 26) 136#define S3C2410_GPC14_VD6 (0x02 << 28) 137#define S3C2410_GPC15_VD7 (0x02 << 30) 138#define S3C2410_GPC_PUPDIS(x) (1<<(x)) 139 140/* 141 * S3C2410: Port D consists of 16 GPIO/Special function 142 * 143 * almost identical setup to port b, but the special functions are mostly 144 * to do with the video system's data. 145 * 146 * almost identical setup to port c 147*/ 148 149#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) 150#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) 151#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) 152 153#define S3C2410_GPD0_VD8 (0x02 << 0) 154#define S3C2442_GPD0_nSPICS1 (0x03 << 0) 155 156#define S3C2410_GPD1_VD9 (0x02 << 2) 157#define S3C2442_GPD1_SPICLK1 (0x03 << 2) 158 159#define S3C2410_GPD2_VD10 (0x02 << 4) 160 161#define S3C2410_GPD3_VD11 (0x02 << 6) 162 163#define S3C2410_GPD4_VD12 (0x02 << 8) 164 165#define S3C2410_GPD5_VD13 (0x02 << 10) 166 167#define S3C2410_GPD6_VD14 (0x02 << 12) 168 169#define S3C2410_GPD7_VD15 (0x02 << 14) 170 171#define S3C2410_GPD8_VD16 (0x02 << 16) 172#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) 173 174#define S3C2410_GPD9_VD17 (0x02 << 18) 175#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) 176 177#define S3C2410_GPD10_VD18 (0x02 << 20) 178#define S3C2440_GPD10_SPICLK1 (0x03 << 20) 179 180#define S3C2410_GPD11_VD19 (0x02 << 22) 181 182#define S3C2410_GPD12_VD20 (0x02 << 24) 183 184#define S3C2410_GPD13_VD21 (0x02 << 26) 185 186#define S3C2410_GPD14_VD22 (0x02 << 28) 187#define S3C2410_GPD14_nSS1 (0x03 << 28) 188 189#define S3C2410_GPD15_VD23 (0x02 << 30) 190#define S3C2410_GPD15_nSS0 (0x03 << 30) 191 192#define S3C2410_GPD_PUPDIS(x) (1<<(x)) 193 194/* S3C2410: 195 * Port E consists of 16 GPIO/Special function 196 * 197 * again, the same as port B, but dealing with I2S, SDI, and 198 * more miscellaneous functions 199 * 200 * GPIO / interrupt inputs 201*/ 202 203#define S3C2410_GPECON S3C2410_GPIOREG(0x40) 204#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) 205#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) 206 207#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 208#define S3C2443_GPE0_AC_nRESET (0x03 << 0) 209#define S3C2410_GPE0_MASK (0x03 << 0) 210 211#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 212#define S3C2443_GPE1_AC_SYNC (0x03 << 2) 213#define S3C2410_GPE1_MASK (0x03 << 2) 214 215#define S3C2410_GPE2_CDCLK (0x02 << 4) 216#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) 217 218#define S3C2410_GPE3_I2SSDI (0x02 << 6) 219#define S3C2443_GPE3_AC_SDI (0x03 << 6) 220#define S3C2410_GPE3_nSS0 (0x03 << 6) 221#define S3C2410_GPE3_MASK (0x03 << 6) 222 223#define S3C2410_GPE4_I2SSDO (0x02 << 8) 224#define S3C2443_GPE4_AC_SDO (0x03 << 8) 225#define S3C2410_GPE4_I2SSDI (0x03 << 8) 226#define S3C2410_GPE4_MASK (0x03 << 8) 227 228#define S3C2410_GPE5_SDCLK (0x02 << 10) 229#define S3C2443_GPE5_SD1_CLK (0x02 << 10) 230#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) 231 232#define S3C2410_GPE6_SDCMD (0x02 << 12) 233#define S3C2443_GPE6_SD1_CMD (0x02 << 12) 234#define S3C2443_GPE6_AC_SDI (0x03 << 12) 235 236#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 237#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) 238#define S3C2443_GPE7_AC_SDO (0x03 << 14) 239 240#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 241#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) 242#define S3C2443_GPE8_AC_SYNC (0x03 << 16) 243 244#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 245#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) 246#define S3C2443_GPE9_AC_nRESET (0x03 << 18) 247 248#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 249#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) 250 251#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 252 253#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) 254 255#define S3C2410_GPE13_SPICLK0 (0x02 << 26) 256 257#define S3C2410_GPE14_IICSCL (0x02 << 28) 258#define S3C2410_GPE14_MASK (0x03 << 28) 259 260#define S3C2410_GPE15_IICSDA (0x02 << 30) 261#define S3C2410_GPE15_MASK (0x03 << 30) 262 263#define S3C2440_GPE0_ACSYNC (0x03 << 0) 264#define S3C2440_GPE1_ACBITCLK (0x03 << 2) 265#define S3C2440_GPE2_ACRESET (0x03 << 4) 266#define S3C2440_GPE3_ACIN (0x03 << 6) 267#define S3C2440_GPE4_ACOUT (0x03 << 8) 268 269#define S3C2410_GPE_PUPDIS(x) (1<<(x)) 270 271/* S3C2410: 272 * Port F consists of 8 GPIO/Special function 273 * 274 * GPIO / interrupt inputs 275 * 276 * GPFCON has 2 bits for each of the input pins on port F 277 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined 278 * 279 * pull up works like all other ports. 280 * 281 * GPIO/serial/misc pins 282*/ 283 284#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) 285#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) 286#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) 287 288#define S3C2410_GPF0_EINT0 (0x02 << 0) 289#define S3C2410_GPF1_EINT1 (0x02 << 2) 290#define S3C2410_GPF2_EINT2 (0x02 << 4) 291#define S3C2410_GPF3_EINT3 (0x02 << 6) 292#define S3C2410_GPF4_EINT4 (0x02 << 8) 293#define S3C2410_GPF5_EINT5 (0x02 << 10) 294#define S3C2410_GPF6_EINT6 (0x02 << 12) 295#define S3C2410_GPF7_EINT7 (0x02 << 14) 296#define S3C2410_GPF_PUPDIS(x) (1<<(x)) 297 298/* S3C2410: 299 * Port G consists of 8 GPIO/IRQ/Special function 300 * 301 * GPGCON has 2 bits for each of the input pins on port G 302 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 303 * 304 * pull up works like all other ports. 305*/ 306 307#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) 308#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) 309#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) 310 311#define S3C2410_GPG0_EINT8 (0x02 << 0) 312 313#define S3C2410_GPG1_EINT9 (0x02 << 2) 314 315#define S3C2410_GPG2_EINT10 (0x02 << 4) 316#define S3C2410_GPG2_nSS0 (0x03 << 4) 317 318#define S3C2410_GPG3_EINT11 (0x02 << 6) 319#define S3C2410_GPG3_nSS1 (0x03 << 6) 320 321#define S3C2410_GPG4_EINT12 (0x02 << 8) 322#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 323#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) 324 325#define S3C2410_GPG5_EINT13 (0x02 << 10) 326#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ 327 328#define S3C2410_GPG6_EINT14 (0x02 << 12) 329#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 330 331#define S3C2410_GPG7_EINT15 (0x02 << 14) 332#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 333 334#define S3C2410_GPG8_EINT16 (0x02 << 16) 335 336#define S3C2410_GPG9_EINT17 (0x02 << 18) 337 338#define S3C2410_GPG10_EINT18 (0x02 << 20) 339 340#define S3C2410_GPG11_EINT19 (0x02 << 22) 341#define S3C2410_GPG11_TCLK1 (0x03 << 22) 342#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) 343 344#define S3C2410_GPG12_EINT20 (0x02 << 24) 345#define S3C2410_GPG12_XMON (0x03 << 24) 346#define S3C2442_GPG12_nSPICS0 (0x03 << 24) 347#define S3C2443_GPG12_nINPACK (0x03 << 24) 348 349#define S3C2410_GPG13_EINT21 (0x02 << 26) 350#define S3C2410_GPG13_nXPON (0x03 << 26) 351#define S3C2443_GPG13_CF_nREG (0x03 << 26) 352 353#define S3C2410_GPG14_EINT22 (0x02 << 28) 354#define S3C2410_GPG14_YMON (0x03 << 28) 355#define S3C2443_GPG14_CF_RESET (0x03 << 28) 356 357#define S3C2410_GPG15_EINT23 (0x02 << 30) 358#define S3C2410_GPG15_nYPON (0x03 << 30) 359#define S3C2443_GPG15_CF_PWR (0x03 << 30) 360 361#define S3C2410_GPG_PUPDIS(x) (1<<(x)) 362 363/* Port H consists of11 GPIO/serial/Misc pins 364 * 365 * GPHCON has 2 bits for each of the input pins on port H 366 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 367 * 368 * pull up works like all other ports. 369*/ 370 371#define S3C2410_GPHCON S3C2410_GPIOREG(0x70) 372#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) 373#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) 374 375#define S3C2410_GPH0_nCTS0 (0x02 << 0) 376#define S3C2416_GPH0_TXD0 (0x02 << 0) 377 378#define S3C2410_GPH1_nRTS0 (0x02 << 2) 379#define S3C2416_GPH1_RXD0 (0x02 << 2) 380 381#define S3C2410_GPH2_TXD0 (0x02 << 4) 382#define S3C2416_GPH2_TXD1 (0x02 << 4) 383 384#define S3C2410_GPH3_RXD0 (0x02 << 6) 385#define S3C2416_GPH3_RXD1 (0x02 << 6) 386 387#define S3C2410_GPH4_TXD1 (0x02 << 8) 388#define S3C2416_GPH4_TXD2 (0x02 << 8) 389 390#define S3C2410_GPH5_RXD1 (0x02 << 10) 391#define S3C2416_GPH5_RXD2 (0x02 << 10) 392 393#define S3C2410_GPH6_TXD2 (0x02 << 12) 394#define S3C2416_GPH6_TXD3 (0x02 << 12) 395#define S3C2410_GPH6_nRTS1 (0x03 << 12) 396#define S3C2416_GPH6_nRTS2 (0x03 << 12) 397 398#define S3C2410_GPH7_RXD2 (0x02 << 14) 399#define S3C2416_GPH7_RXD3 (0x02 << 14) 400#define S3C2410_GPH7_nCTS1 (0x03 << 14) 401#define S3C2416_GPH7_nCTS2 (0x03 << 14) 402 403#define S3C2410_GPH8_UCLK (0x02 << 16) 404#define S3C2416_GPH8_nCTS0 (0x02 << 16) 405 406#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 407#define S3C2442_GPH9_nSPICS0 (0x03 << 18) 408#define S3C2416_GPH9_nRTS0 (0x02 << 18) 409 410#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 411#define S3C2416_GPH10_nCTS1 (0x02 << 20) 412 413#define S3C2416_GPH11_nRTS1 (0x02 << 22) 414 415#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) 416 417#define S3C2416_GPH13_CLKOUT0 (0x02 << 26) 418 419#define S3C2416_GPH14_CLKOUT1 (0x02 << 28) 420 421/* The S3C2412 and S3C2413 move the GPJ register set to after 422 * GPH, which means all registers after 0x80 are now offset by 0x10 423 * for the 2412/2413 from the 2410/2440/2442 424*/ 425 426/* 427 * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits 428 * for each of the pins on port J. 429 * 00 - input, 01 output, 10 - camera 430 * 431 * Pull up works like all other ports. 432 */ 433 434#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) 435#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) 436#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) 437#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) 438 439/* S3C2443 and above */ 440#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) 441#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) 442#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) 443 444#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) 445#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) 446#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) 447 448#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) 449#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) 450#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) 451 452#define S3C2443_GPMCON S3C2410_GPIOREG(0x100) 453#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) 454#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) 455 456/* miscellaneous control */ 457#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 458 459/* see clock.h for dclk definitions */ 460 461/* pullup control on databus */ 462#define S3C2410_MISCCR_SPUCR_HEN (0<<0) 463#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) 464#define S3C2410_MISCCR_SPUCR_LEN (0<<1) 465#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) 466 467#define S3C2410_MISCCR_USBDEV (0<<3) 468#define S3C2410_MISCCR_USBHOST (1<<3) 469 470#define S3C2410_MISCCR_CLK0_MPLL (0<<4) 471#define S3C2410_MISCCR_CLK0_UPLL (1<<4) 472#define S3C2410_MISCCR_CLK0_FCLK (2<<4) 473#define S3C2410_MISCCR_CLK0_HCLK (3<<4) 474#define S3C2410_MISCCR_CLK0_PCLK (4<<4) 475#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) 476#define S3C2410_MISCCR_CLK0_MASK (7<<4) 477 478#define S3C2412_MISCCR_CLK0_RTC (2<<4) 479 480#define S3C2410_MISCCR_CLK1_MPLL (0<<8) 481#define S3C2410_MISCCR_CLK1_UPLL (1<<8) 482#define S3C2410_MISCCR_CLK1_FCLK (2<<8) 483#define S3C2410_MISCCR_CLK1_HCLK (3<<8) 484#define S3C2410_MISCCR_CLK1_PCLK (4<<8) 485#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) 486#define S3C2410_MISCCR_CLK1_MASK (7<<8) 487 488#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) 489 490#define S3C2410_MISCCR_USBSUSPND0 (1<<12) 491#define S3C2416_MISCCR_SEL_SUSPND (1<<12) 492#define S3C2410_MISCCR_USBSUSPND1 (1<<13) 493 494#define S3C2410_MISCCR_nRSTCON (1<<16) 495 496#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) 497#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) 498#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ 499#define S3C2410_MISCCR_SDSLEEP (7<<17) 500 501#define S3C2416_MISCCR_FLT_I2C (1<<24) 502#define S3C2416_MISCCR_HSSPI_EN2 (1<<31) 503 504/* external interrupt control... */ 505/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 506 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 507 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 508 * 509 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 510 * 511 * Samsung datasheet p9-25 512*/ 513#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) 514#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 515#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 516 517#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) 518#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) 519#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) 520 521/* interrupt filtering control for EINT16..EINT23 */ 522#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) 523#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) 524#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) 525#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) 526 527#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) 528#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) 529#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) 530#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) 531 532/* values for interrupt filtering */ 533#define S3C2410_EINTFLT_PCLK (0x00) 534#define S3C2410_EINTFLT_EXTCLK (1<<7) 535#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) 536 537/* removed EINTxxxx defs from here, not meant for this */ 538 539/* GSTATUS have miscellaneous information in them 540 * 541 * These move between s3c2410 and s3c2412 style systems. 542 */ 543 544#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) 545#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) 546#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) 547#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) 548#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) 549 550#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) 551#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) 552#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) 553#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) 554#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) 555 556#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) 557#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) 558#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) 559#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) 560#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) 561 562#define S3C2410_GSTATUS0_nWAIT (1<<3) 563#define S3C2410_GSTATUS0_NCON (1<<2) 564#define S3C2410_GSTATUS0_RnB (1<<1) 565#define S3C2410_GSTATUS0_nBATTFLT (1<<0) 566 567#define S3C2410_GSTATUS1_IDMASK (0xffff0000) 568#define S3C2410_GSTATUS1_2410 (0x32410000) 569#define S3C2410_GSTATUS1_2412 (0x32412001) 570#define S3C2410_GSTATUS1_2416 (0x32416003) 571#define S3C2410_GSTATUS1_2440 (0x32440000) 572#define S3C2410_GSTATUS1_2442 (0x32440aaa) 573/* some 2416 CPUs report this value also */ 574#define S3C2410_GSTATUS1_2450 (0x32450003) 575 576#define S3C2410_GSTATUS2_WTRESET (1<<2) 577#define S3C2410_GSTATUS2_OFFRESET (1<<1) 578#define S3C2410_GSTATUS2_PONRESET (1<<0) 579 580/* 2412/2413 sleep configuration registers */ 581 582#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) 583#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) 584#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) 585#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) 586#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) 587#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) 588 589/* definitions for each pin bit */ 590#define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) 591#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) 592#define S3C2412_GPIO_SLPCON_IN ( 0x02 ) 593#define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) 594 595#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) 596#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) 597#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) 598#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) 599#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ 600#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) 601 602#define S3C2412_SLPCON_ALL_LOW (0x0) 603#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) 604#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) 605#define S3C2412_SLPCON_ALL_PULL (0x33333333) 606 607#endif /* __ASM_ARCH_REGS_GPIO_H */ 608