cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

regs-irq-s3c24xx.h (1780B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
      4 *		      http://www.simtec.co.uk/products/SWLINUX/
      5 */
      6
      7
      8#ifndef ___ASM_ARCH_REGS_IRQ_H
      9#define ___ASM_ARCH_REGS_IRQ_H
     10
     11#include "map-s3c.h"
     12
     13/* interrupt controller */
     14
     15#define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
     16#define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
     17#define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)
     18
     19#define S3C2410_SRCPND	       S3C2410_IRQREG(0x000)
     20#define S3C2410_INTMOD	       S3C2410_IRQREG(0x004)
     21#define S3C2410_INTMSK	       S3C2410_IRQREG(0x008)
     22#define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
     23#define S3C2410_INTPND	       S3C2410_IRQREG(0x010)
     24#define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
     25#define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
     26#define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
     27
     28#define S3C2416_PRIORITY_MODE1		S3C2410_IRQREG(0x030)
     29#define S3C2416_PRIORITY_UPDATE1	S3C2410_IRQREG(0x034)
     30#define S3C2416_SRCPND2			S3C2410_IRQREG(0x040)
     31#define S3C2416_INTMOD2			S3C2410_IRQREG(0x044)
     32#define S3C2416_INTMSK2			S3C2410_IRQREG(0x048)
     33#define S3C2416_INTPND2			S3C2410_IRQREG(0x050)
     34#define S3C2416_INTOFFSET2		S3C2410_IRQREG(0x054)
     35#define S3C2416_PRIORITY_MODE2		S3C2410_IRQREG(0x070)
     36#define S3C2416_PRIORITY_UPDATE2	S3C2410_IRQREG(0x074)
     37
     38/* mask: 0=enable, 1=disable
     39 * 1 bit EINT, 4=EINT4, 23=EINT23
     40 * EINT0,1,2,3 are not handled here.
     41*/
     42
     43#define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
     44#define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
     45#define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
     46#define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)
     47
     48#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
     49#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)
     50
     51#endif /* ___ASM_ARCH_REGS_IRQ_H */