cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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setup-ide-s3c64xx.c (1061B)

      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// Copyright (c) 2010 Samsung Electronics Co., Ltd.
      4//		http://www.samsung.com/
      5//
      6// S3C64XX setup information for IDE
      7
      8#include <linux/kernel.h>
      9#include <linux/gpio.h>
     10#include <linux/io.h>
     11
     12#include <linux/platform_data/ata-samsung_cf.h>
     13
     14#include "map.h"
     15#include "regs-clock.h"
     16#include "gpio-cfg.h"
     17#include "gpio-samsung.h"
     18
     19void s3c64xx_ide_setup_gpio(void)
     20{
     21	u32 reg;
     22
     23	reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
     24
     25	/* Independent CF interface, CF chip select configuration */
     26	writel(reg | MEM_SYS_CFG_INDEP_CF |
     27		MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
     28
     29	s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
     30
     31	/* Set XhiDATA[15:0] pins as CF Data[15:0] */
     32	s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
     33
     34	/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
     35	s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
     36
     37	/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
     38	s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
     39	s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
     40}