cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sleep-s3c24xx.S (1470B)


      1/* SPDX-License-Identifier: GPL-2.0+ */
      2/*
      3 * Copyright (c) 2004 Simtec Electronics
      4 *	Ben Dooks <ben@simtec.co.uk>
      5 *
      6 * S3C2410 Power Manager (Suspend-To-RAM) support
      7 *
      8 * Based on PXA/SA1100 sleep code by:
      9 *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
     10 *	Cliff Brake, (c) 2001
     11 */
     12
     13#include <linux/linkage.h>
     14#include <linux/serial_s3c.h>
     15#include <asm/assembler.h>
     16#include "map.h"
     17
     18#include "regs-gpio.h"
     19#include "regs-clock.h"
     20
     21/*
     22 * S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not
     23 * reset the UART configuration, only enable if you really need this!
     24 */
     25//#define S3C24XX_DEBUG_RESUME
     26
     27	.text
     28
     29	/* sleep magic, to allow the bootloader to check for an valid
     30	 * image to resume to. Must be the first word before the
     31	 * s3c_cpu_resume entry.
     32	*/
     33
     34	.word	0x2bedf00d
     35
     36	/* s3c_cpu_resume
     37	 *
     38	 * resume code entry for bootloader to call
     39	*/
     40
     41ENTRY(s3c_cpu_resume)
     42	mov	r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
     43	msr	cpsr_c, r0
     44
     45	@@ load UART to allow us to print the two characters for
     46	@@ resume debug
     47
     48	mov	r2, #S3C24XX_PA_UART & 0xff000000
     49	orr	r2, r2, #S3C24XX_PA_UART & 0xff000
     50
     51#if 0
     52	/* SMDK2440 LED set */
     53	mov	r14, #S3C24XX_PA_GPIO
     54	ldr	r12, [ r14, #0x54 ]
     55	bic	r12, r12, #3<<4
     56	orr	r12, r12, #1<<7
     57	str	r12, [ r14, #0x54 ]
     58#endif
     59
     60#ifdef S3C24XX_DEBUG_RESUME
     61	mov	r3, #'L'
     62	strb	r3, [ r2, #S3C2410_UTXH ]
     631001:
     64	ldrb	r14, [ r3, #S3C2410_UTRSTAT ]
     65	tst	r14, #S3C2410_UTRSTAT_TXE
     66	beq	1001b
     67#endif /* S3C24XX_DEBUG_RESUME */
     68
     69	b	cpu_resume