core.h (1154B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright 2012 Pavel Machek <pavel@denx.de> 4 * Copyright (C) 2012-2015 Altera Corporation 5 */ 6 7#ifndef __MACH_CORE_H 8#define __MACH_CORE_H 9 10#define SOCFPGA_RSTMGR_CTRL 0x04 11#define SOCFPGA_RSTMGR_MODMPURST 0x10 12#define SOCFPGA_RSTMGR_MODPERRST 0x14 13#define SOCFPGA_RSTMGR_BRGMODRST 0x1c 14 15#define SOCFPGA_A10_RSTMGR_CTRL 0xC 16#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 17 18/* System Manager bits */ 19#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ 20#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ 21 22#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ 23 24void socfpga_init_l2_ecc(void); 25void socfpga_init_ocram_ecc(void); 26void socfpga_init_arria10_l2_ecc(void); 27void socfpga_init_arria10_ocram_ecc(void); 28 29extern void __iomem *sys_manager_base_addr; 30extern void __iomem *rst_manager_base_addr; 31extern void __iomem *sdr_ctl_base_addr; 32 33u32 socfpga_sdram_self_refresh(u32 sdr_base); 34extern unsigned int socfpga_sdram_self_refresh_sz; 35 36extern char secondary_trampoline[], secondary_trampoline_end[]; 37 38extern unsigned long socfpga_cpu1start_addr; 39 40#define SOCFPGA_SCU_VIRT_BASE 0xfee00000 41 42#endif