cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spear320.c (5973B)


      1/*
      2 * arch/arm/mach-spear3xx/spear320.c
      3 *
      4 * SPEAr320 machine source file
      5 *
      6 * Copyright (C) 2009-2012 ST Microelectronics
      7 * Viresh Kumar <vireshk@kernel.org>
      8 *
      9 * This file is licensed under the terms of the GNU General Public
     10 * License version 2. This program is licensed "as is" without any
     11 * warranty of any kind, whether express or implied.
     12 */
     13
     14#define pr_fmt(fmt) "SPEAr320: " fmt
     15
     16#include <linux/amba/pl022.h>
     17#include <linux/amba/pl08x.h>
     18#include <linux/amba/serial.h>
     19#include <linux/of_platform.h>
     20#include <asm/mach/arch.h>
     21#include <asm/mach/map.h>
     22#include "generic.h"
     23#include "spear.h"
     24
     25#define SPEAR320_UART1_BASE		UL(0xA3000000)
     26#define SPEAR320_UART2_BASE		UL(0xA4000000)
     27#define SPEAR320_SSP0_BASE		UL(0xA5000000)
     28#define SPEAR320_SSP1_BASE		UL(0xA6000000)
     29
     30/* DMAC platform data's slave info */
     31struct pl08x_channel_data spear320_dma_info[] = {
     32	{
     33		.bus_id = "uart0_rx",
     34		.min_signal = 2,
     35		.max_signal = 2,
     36		.muxval = 0,
     37		.periph_buses = PL08X_AHB1,
     38	}, {
     39		.bus_id = "uart0_tx",
     40		.min_signal = 3,
     41		.max_signal = 3,
     42		.muxval = 0,
     43		.periph_buses = PL08X_AHB1,
     44	}, {
     45		.bus_id = "ssp0_rx",
     46		.min_signal = 8,
     47		.max_signal = 8,
     48		.muxval = 0,
     49		.periph_buses = PL08X_AHB1,
     50	}, {
     51		.bus_id = "ssp0_tx",
     52		.min_signal = 9,
     53		.max_signal = 9,
     54		.muxval = 0,
     55		.periph_buses = PL08X_AHB1,
     56	}, {
     57		.bus_id = "i2c0_rx",
     58		.min_signal = 10,
     59		.max_signal = 10,
     60		.muxval = 0,
     61		.periph_buses = PL08X_AHB1,
     62	}, {
     63		.bus_id = "i2c0_tx",
     64		.min_signal = 11,
     65		.max_signal = 11,
     66		.muxval = 0,
     67		.periph_buses = PL08X_AHB1,
     68	}, {
     69		.bus_id = "irda",
     70		.min_signal = 12,
     71		.max_signal = 12,
     72		.muxval = 0,
     73		.periph_buses = PL08X_AHB1,
     74	}, {
     75		.bus_id = "adc",
     76		.min_signal = 13,
     77		.max_signal = 13,
     78		.muxval = 0,
     79		.periph_buses = PL08X_AHB1,
     80	}, {
     81		.bus_id = "to_jpeg",
     82		.min_signal = 14,
     83		.max_signal = 14,
     84		.muxval = 0,
     85		.periph_buses = PL08X_AHB1,
     86	}, {
     87		.bus_id = "from_jpeg",
     88		.min_signal = 15,
     89		.max_signal = 15,
     90		.muxval = 0,
     91		.periph_buses = PL08X_AHB1,
     92	}, {
     93		.bus_id = "ssp1_rx",
     94		.min_signal = 0,
     95		.max_signal = 0,
     96		.muxval = 1,
     97		.periph_buses = PL08X_AHB2,
     98	}, {
     99		.bus_id = "ssp1_tx",
    100		.min_signal = 1,
    101		.max_signal = 1,
    102		.muxval = 1,
    103		.periph_buses = PL08X_AHB2,
    104	}, {
    105		.bus_id = "ssp2_rx",
    106		.min_signal = 2,
    107		.max_signal = 2,
    108		.muxval = 1,
    109		.periph_buses = PL08X_AHB2,
    110	}, {
    111		.bus_id = "ssp2_tx",
    112		.min_signal = 3,
    113		.max_signal = 3,
    114		.muxval = 1,
    115		.periph_buses = PL08X_AHB2,
    116	}, {
    117		.bus_id = "uart1_rx",
    118		.min_signal = 4,
    119		.max_signal = 4,
    120		.muxval = 1,
    121		.periph_buses = PL08X_AHB2,
    122	}, {
    123		.bus_id = "uart1_tx",
    124		.min_signal = 5,
    125		.max_signal = 5,
    126		.muxval = 1,
    127		.periph_buses = PL08X_AHB2,
    128	}, {
    129		.bus_id = "uart2_rx",
    130		.min_signal = 6,
    131		.max_signal = 6,
    132		.muxval = 1,
    133		.periph_buses = PL08X_AHB2,
    134	}, {
    135		.bus_id = "uart2_tx",
    136		.min_signal = 7,
    137		.max_signal = 7,
    138		.muxval = 1,
    139		.periph_buses = PL08X_AHB2,
    140	}, {
    141		.bus_id = "i2c1_rx",
    142		.min_signal = 8,
    143		.max_signal = 8,
    144		.muxval = 1,
    145		.periph_buses = PL08X_AHB2,
    146	}, {
    147		.bus_id = "i2c1_tx",
    148		.min_signal = 9,
    149		.max_signal = 9,
    150		.muxval = 1,
    151		.periph_buses = PL08X_AHB2,
    152	}, {
    153		.bus_id = "i2c2_rx",
    154		.min_signal = 10,
    155		.max_signal = 10,
    156		.muxval = 1,
    157		.periph_buses = PL08X_AHB2,
    158	}, {
    159		.bus_id = "i2c2_tx",
    160		.min_signal = 11,
    161		.max_signal = 11,
    162		.muxval = 1,
    163		.periph_buses = PL08X_AHB2,
    164	}, {
    165		.bus_id = "i2s_rx",
    166		.min_signal = 12,
    167		.max_signal = 12,
    168		.muxval = 1,
    169		.periph_buses = PL08X_AHB2,
    170	}, {
    171		.bus_id = "i2s_tx",
    172		.min_signal = 13,
    173		.max_signal = 13,
    174		.muxval = 1,
    175		.periph_buses = PL08X_AHB2,
    176	}, {
    177		.bus_id = "rs485_rx",
    178		.min_signal = 14,
    179		.max_signal = 14,
    180		.muxval = 1,
    181		.periph_buses = PL08X_AHB2,
    182	}, {
    183		.bus_id = "rs485_tx",
    184		.min_signal = 15,
    185		.max_signal = 15,
    186		.muxval = 1,
    187		.periph_buses = PL08X_AHB2,
    188	},
    189};
    190
    191static struct pl022_ssp_controller spear320_ssp_data[] = {
    192	{
    193		.bus_id = 1,
    194		.enable_dma = 1,
    195		.dma_filter = pl08x_filter_id,
    196		.dma_tx_param = "ssp1_tx",
    197		.dma_rx_param = "ssp1_rx",
    198	}, {
    199		.bus_id = 2,
    200		.enable_dma = 1,
    201		.dma_filter = pl08x_filter_id,
    202		.dma_tx_param = "ssp2_tx",
    203		.dma_rx_param = "ssp2_rx",
    204	}
    205};
    206
    207static struct amba_pl011_data spear320_uart_data[] = {
    208	{
    209		.dma_filter = pl08x_filter_id,
    210		.dma_tx_param = "uart1_tx",
    211		.dma_rx_param = "uart1_rx",
    212	}, {
    213		.dma_filter = pl08x_filter_id,
    214		.dma_tx_param = "uart2_tx",
    215		.dma_rx_param = "uart2_rx",
    216	},
    217};
    218
    219/* Add SPEAr310 auxdata to pass platform data */
    220static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
    221	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
    222			&pl022_plat_data),
    223	OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
    224			&pl080_plat_data),
    225	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
    226			&spear320_ssp_data[0]),
    227	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
    228			&spear320_ssp_data[1]),
    229	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
    230			&spear320_uart_data[0]),
    231	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
    232			&spear320_uart_data[1]),
    233	{}
    234};
    235
    236static void __init spear320_dt_init(void)
    237{
    238	pl080_plat_data.slave_channels = spear320_dma_info;
    239	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
    240
    241	of_platform_default_populate(NULL, spear320_auxdata_lookup, NULL);
    242}
    243
    244static const char * const spear320_dt_board_compat[] = {
    245	"st,spear320",
    246	"st,spear320-evb",
    247	"st,spear320-hmi",
    248	NULL,
    249};
    250
    251struct map_desc spear320_io_desc[] __initdata = {
    252	{
    253		.virtual	= (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE,
    254		.pfn		= __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
    255		.length		= SZ_16M,
    256		.type		= MT_DEVICE
    257	},
    258};
    259
    260static void __init spear320_map_io(void)
    261{
    262	iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
    263	spear3xx_map_io();
    264}
    265
    266DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
    267	.map_io		=	spear320_map_io,
    268	.init_time	=	spear3xx_timer_init,
    269	.init_machine	=	spear320_dt_init,
    270	.restart	=	spear_restart,
    271	.dt_compat	=	spear320_dt_board_compat,
    272MACHINE_END