iomap.h (3437B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2010 Google, Inc. 4 * 5 * Author: 6 * Colin Cross <ccross@google.com> 7 * Erik Gilling <konkers@google.com> 8 */ 9 10#ifndef __MACH_TEGRA_IOMAP_H 11#define __MACH_TEGRA_IOMAP_H 12 13#include <linux/pgtable.h> 14#include <linux/sizes.h> 15 16#define TEGRA_IRAM_BASE 0x40000000 17#define TEGRA_IRAM_SIZE SZ_256K 18 19#define TEGRA_ARM_PERIF_BASE 0x50040000 20#define TEGRA_ARM_PERIF_SIZE SZ_8K 21 22#define TEGRA_ARM_INT_DIST_BASE 0x50041000 23#define TEGRA_ARM_INT_DIST_SIZE SZ_4K 24 25#define TEGRA_TMR1_BASE 0x60005000 26#define TEGRA_TMR1_SIZE SZ_8 27 28#define TEGRA_TMR2_BASE 0x60005008 29#define TEGRA_TMR2_SIZE SZ_8 30 31#define TEGRA_TMRUS_BASE 0x60005010 32#define TEGRA_TMRUS_SIZE SZ_64 33 34#define TEGRA_TMR3_BASE 0x60005050 35#define TEGRA_TMR3_SIZE SZ_8 36 37#define TEGRA_TMR4_BASE 0x60005058 38#define TEGRA_TMR4_SIZE SZ_8 39 40#define TEGRA_CLK_RESET_BASE 0x60006000 41#define TEGRA_CLK_RESET_SIZE SZ_4K 42 43#define TEGRA_FLOW_CTRL_BASE 0x60007000 44#define TEGRA_FLOW_CTRL_SIZE 20 45 46#define TEGRA_SB_BASE 0x6000C200 47#define TEGRA_SB_SIZE 256 48 49#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 50#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K 51 52#define TEGRA_APB_MISC_BASE 0x70000000 53#define TEGRA_APB_MISC_SIZE SZ_4K 54 55#define TEGRA_UARTA_BASE 0x70006000 56#define TEGRA_UARTA_SIZE SZ_64 57 58#define TEGRA_UARTB_BASE 0x70006040 59#define TEGRA_UARTB_SIZE SZ_64 60 61#define TEGRA_UARTC_BASE 0x70006200 62#define TEGRA_UARTC_SIZE SZ_256 63 64#define TEGRA_UARTD_BASE 0x70006300 65#define TEGRA_UARTD_SIZE SZ_256 66 67#define TEGRA_UARTE_BASE 0x70006400 68#define TEGRA_UARTE_SIZE SZ_256 69 70#define TEGRA_PMC_BASE 0x7000E400 71#define TEGRA_PMC_SIZE SZ_256 72 73#define TEGRA_EMC_BASE 0x7000F400 74#define TEGRA_EMC_SIZE SZ_1K 75 76#define TEGRA_EMC0_BASE 0x7001A000 77#define TEGRA_EMC0_SIZE SZ_2K 78 79#define TEGRA_EMC1_BASE 0x7001A800 80#define TEGRA_EMC1_SIZE SZ_2K 81 82#define TEGRA124_EMC_BASE 0x7001B000 83#define TEGRA124_EMC_SIZE SZ_2K 84 85#define TEGRA_CSITE_BASE 0x70040000 86#define TEGRA_CSITE_SIZE SZ_256K 87 88/* On TEGRA, many peripherals are very closely packed in 89 * two 256MB io windows (that actually only use about 64KB 90 * at the start of each). 91 * 92 * We will just map the first MMU section of each window (to minimize 93 * pt entries needed) and provide a macro to transform physical 94 * io addresses to an appropriate void __iomem *. 95 */ 96 97#define IO_IRAM_PHYS 0x40000000 98#define IO_IRAM_VIRT IOMEM(0xFE400000) 99#define IO_IRAM_SIZE SZ_256K 100 101#define IO_CPU_PHYS 0x50040000 102#define IO_CPU_VIRT IOMEM(0xFE440000) 103#define IO_CPU_SIZE SZ_16K 104 105#define IO_PPSB_PHYS 0x60000000 106#define IO_PPSB_VIRT IOMEM(0xFE200000) 107#define IO_PPSB_SIZE SECTION_SIZE 108 109#define IO_APB_PHYS 0x70000000 110#define IO_APB_VIRT IOMEM(0xFE000000) 111#define IO_APB_SIZE SECTION_SIZE 112 113#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 114#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 115 116#define IO_TO_VIRT(n) ( \ 117 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \ 118 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \ 119 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \ 120 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \ 121 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \ 122 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \ 123 IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \ 124 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \ 125 NULL) 126 127#define IO_ADDRESS(n) (IO_TO_VIRT(n)) 128 129#endif