cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcscb_setup.S (829B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Created by:  Dave Martin, 2012-06-22
      4 * Copyright:   (C) 2012-2013  Linaro Limited
      5 */
      6
      7#include <linux/linkage.h>
      8
      9
     10ENTRY(dcscb_power_up_setup)
     11
     12	cmp	r0, #0			@ check affinity level
     13	beq	2f
     14
     15/*
     16 * Enable cluster-level coherency, in preparation for turning on the MMU.
     17 * The ACTLR SMP bit does not need to be set here, because cpu_resume()
     18 * already restores that.
     19 *
     20 * A15/A7 may not require explicit L2 invalidation on reset, dependent
     21 * on hardware integration decisions.
     22 * For now, this code assumes that L2 is either already invalidated,
     23 * or invalidation is not required.
     24 */
     25
     26	b	cci_enable_port_for_self
     27
     282:	@ Implementation-specific local CPU setup operations should go here,
     29	@ if any.  In this case, there is nothing to do.
     30
     31	bx	lr
     32
     33ENDPROC(dcscb_power_up_setup)