cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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headsmp.S (821B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  Copyright (c) 2003 ARM Limited
      4 *  All Rights Reserved
      5 */
      6#include <linux/linkage.h>
      7#include <linux/init.h>
      8#include <asm/assembler.h>
      9
     10/*
     11 * Realview/Versatile Express specific entry point for secondary CPUs.
     12 * This provides a "holding pen" into which all secondary cores are held
     13 * until we're ready for them to initialise.
     14 */
     15ENTRY(versatile_secondary_startup)
     16 ARM_BE8(setend	be)
     17	mrc	p15, 0, r0, c0, c0, 5
     18	bic	r0, #0xff000000
     19	adr	r4, 1f
     20	ldmia	r4, {r5, r6}
     21	sub	r4, r4, r5
     22	add	r6, r6, r4
     23pen:	ldr	r7, [r6]
     24	cmp	r7, r0
     25	bne	pen
     26
     27	/*
     28	 * we've been released from the holding pen: secondary_stack
     29	 * should now contain the SVC stack for this core
     30	 */
     31	b	secondary_startup
     32
     33	.align
     341:	.long	.
     35	.long	versatile_cpu_release
     36ENDPROC(versatile_secondary_startup)