cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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common.h (1123B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * This file contains common function prototypes to avoid externs
      4 * in the c files.
      5 *
      6 *  Copyright (C) 2011 Xilinx
      7 */
      8
      9#ifndef __MACH_ZYNQ_COMMON_H__
     10#define __MACH_ZYNQ_COMMON_H__
     11
     12extern int zynq_slcr_init(void);
     13extern int zynq_early_slcr_init(void);
     14extern void zynq_slcr_cpu_stop(int cpu);
     15extern void zynq_slcr_cpu_start(int cpu);
     16extern bool zynq_slcr_cpu_state_read(int cpu);
     17extern void zynq_slcr_cpu_state_write(int cpu, bool die);
     18extern u32 zynq_slcr_get_device_id(void);
     19
     20#ifdef CONFIG_SMP
     21extern char zynq_secondary_trampoline;
     22extern char zynq_secondary_trampoline_jump;
     23extern char zynq_secondary_trampoline_end;
     24extern int zynq_cpun_start(u32 address, int cpu);
     25extern const struct smp_operations zynq_smp_ops;
     26#endif
     27
     28extern void __iomem *zynq_scu_base;
     29
     30void zynq_pm_late_init(void);
     31
     32static inline void zynq_core_pm_init(void)
     33{
     34	/* A9 clock gating */
     35	asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"
     36		      "orr  r12, r12, #1\n"
     37		      "mcr  p15, 0, r12, c15, c0, 0\n"
     38		      : /* no outputs */
     39		      : /* no inputs */
     40		      : "r12");
     41}
     42
     43#endif