cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun50i-a64-pinephone-1.2.dts (1371B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
      3
      4/dts-v1/;
      5
      6#include "sun50i-a64-pinephone.dtsi"
      7
      8/ {
      9	model = "Pine64 PinePhone (1.2)";
     10	compatible = "pine64,pinephone-1.2", "pine64,pinephone", "allwinner,sun50i-a64";
     11
     12	wifi_pwrseq: wifi-pwrseq {
     13		compatible = "mmc-pwrseq-simple";
     14		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
     15	};
     16};
     17
     18&backlight {
     19	power-supply = <&reg_ldo_io0>;
     20	/*
     21	 * PWM backlight circuit on this PinePhone revision was changed since 1.0,
     22	 * and the lowest PWM duty cycle that doesn't lead to backlight being off
     23	 * is around 10%. Duty cycle for the lowest brightness level also varries
     24	 * quite a bit between individual boards, so the lowest value here was
     25	 * chosen as a safe default.
     26	 */
     27	brightness-levels = <
     28		5000 5248 5506 5858 6345
     29		6987 7805 8823 10062 11543
     30		13287 15317 17654 20319 23336
     31		26724 30505 34702 39335 44427
     32		50000
     33	>;
     34	num-interpolated-steps = <50>;
     35	default-brightness-level = <500>;
     36};
     37
     38&lis3mdl {
     39	/*
     40	 * Board revision 1.2 fixed routing of the interrupt to DRDY pin,
     41	 * enable interrupts.
     42	 */
     43	interrupt-parent = <&pio>;
     44	interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */
     45};
     46
     47&mmc1 {
     48	mmc-pwrseq = <&wifi_pwrseq>;
     49};
     50
     51&sgm3140 {
     52	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
     53	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
     54};