cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun50i-h5-libretech-all-h5-cc.dts (1250B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
      3
      4#include "sun50i-h5-libretech-all-h3-cc.dts"
      5
      6/ {
      7	model = "Libre Computer Board ALL-H5-CC H5";
      8	compatible = "libretech,all-h5-cc-h5", "allwinner,sun50i-h5";
      9
     10	aliases {
     11		spi0 = &spi0;
     12	};
     13
     14	reg_gmac_3v3: gmac-3v3 {
     15		compatible = "regulator-fixed";
     16		regulator-name = "gmac-3v3";
     17		regulator-min-microvolt = <3300000>;
     18		regulator-max-microvolt = <3300000>;
     19		startup-delay-us = <5000>;
     20		enable-active-high;
     21		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
     22		vin-supply = <&reg_vcc5v0>;
     23	};
     24};
     25
     26&codec {
     27	/* No line out; only onboard microphone */
     28	allwinner,audio-routing =
     29		"MIC1", "Mic",
     30		"Mic",  "MBIAS";
     31};
     32
     33/* This board has external PHY */
     34&emac {
     35	pinctrl-names = "default";
     36	pinctrl-0 = <&emac_rgmii_pins>;
     37	phy-supply = <&reg_gmac_3v3>;
     38	phy-handle = <&ext_rgmii_phy>;
     39	phy-mode = "rgmii-id";
     40	/delete-property/ allwinner,leds-active-low;
     41	status = "okay";
     42};
     43
     44&external_mdio {
     45	ext_rgmii_phy: ethernet-phy@1 {
     46		compatible = "ethernet-phy-ieee802.3-c22";
     47		reg = <1>;
     48	};
     49};
     50
     51&spi0  {
     52	status = "okay";
     53
     54	flash@0 {
     55		#address-cells = <1>;
     56		#size-cells = <1>;
     57		compatible = "jedec,spi-nor";
     58		reg = <0>;
     59		spi-max-frequency = <50000000>;
     60	};
     61};