amd-seattle-cpus.dtsi (4141B)
1// SPDX-License-Identifier: GPL-2.0 2 3/ { 4 cpus { 5 #address-cells = <0x1>; 6 #size-cells = <0x0>; 7 8 cpu-map { 9 cluster0 { 10 core0 { 11 cpu = <&CPU0>; 12 }; 13 core1 { 14 cpu = <&CPU1>; 15 }; 16 }; 17 cluster1 { 18 core0 { 19 cpu = <&CPU2>; 20 }; 21 core1 { 22 cpu = <&CPU3>; 23 }; 24 }; 25 cluster2 { 26 core0 { 27 cpu = <&CPU4>; 28 }; 29 core1 { 30 cpu = <&CPU5>; 31 }; 32 }; 33 cluster3 { 34 core0 { 35 cpu = <&CPU6>; 36 }; 37 core1 { 38 cpu = <&CPU7>; 39 }; 40 }; 41 }; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a57"; 46 reg = <0x0>; 47 enable-method = "psci"; 48 49 i-cache-size = <0xC000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <256>; 55 l2-cache = <&L2_0>; 56 57 }; 58 59 CPU1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a57"; 62 reg = <0x1>; 63 enable-method = "psci"; 64 65 i-cache-size = <0xC000>; 66 i-cache-line-size = <64>; 67 i-cache-sets = <256>; 68 d-cache-size = <0x8000>; 69 d-cache-line-size = <64>; 70 d-cache-sets = <256>; 71 l2-cache = <&L2_0>; 72 }; 73 74 CPU2: cpu@100 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a57"; 77 reg = <0x100>; 78 enable-method = "psci"; 79 80 i-cache-size = <0xC000>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <256>; 83 d-cache-size = <0x8000>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <256>; 86 l2-cache = <&L2_1>; 87 }; 88 89 CPU3: cpu@101 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a57"; 92 reg = <0x101>; 93 enable-method = "psci"; 94 95 i-cache-size = <0xC000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <256>; 101 l2-cache = <&L2_1>; 102 }; 103 104 CPU4: cpu@200 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a57"; 107 reg = <0x200>; 108 enable-method = "psci"; 109 110 i-cache-size = <0xC000>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <256>; 113 d-cache-size = <0x8000>; 114 d-cache-line-size = <64>; 115 d-cache-sets = <256>; 116 l2-cache = <&L2_2>; 117 }; 118 119 CPU5: cpu@201 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a57"; 122 reg = <0x201>; 123 enable-method = "psci"; 124 125 i-cache-size = <0xC000>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <256>; 128 d-cache-size = <0x8000>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <256>; 131 l2-cache = <&L2_2>; 132 }; 133 134 CPU6: cpu@300 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a57"; 137 reg = <0x300>; 138 enable-method = "psci"; 139 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <256>; 143 d-cache-size = <0x8000>; 144 d-cache-line-size = <64>; 145 d-cache-sets = <256>; 146 l2-cache = <&L2_3>; 147 }; 148 149 CPU7: cpu@301 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a57"; 152 reg = <0x301>; 153 enable-method = "psci"; 154 155 i-cache-size = <0xC000>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <256>; 158 d-cache-size = <0x8000>; 159 d-cache-line-size = <64>; 160 d-cache-sets = <256>; 161 l2-cache = <&L2_3>; 162 }; 163 }; 164 165 L2_0: l2-cache0 { 166 cache-size = <0x100000>; 167 cache-line-size = <64>; 168 cache-sets = <1024>; 169 cache-unified; 170 next-level-cache = <&L3>; 171 }; 172 173 L2_1: l2-cache1 { 174 cache-size = <0x100000>; 175 cache-line-size = <64>; 176 cache-sets = <1024>; 177 cache-unified; 178 next-level-cache = <&L3>; 179 }; 180 181 L2_2: l2-cache2 { 182 cache-size = <0x100000>; 183 cache-line-size = <64>; 184 cache-sets = <1024>; 185 cache-unified; 186 next-level-cache = <&L3>; 187 }; 188 189 L2_3: l2-cache3 { 190 cache-size = <0x100000>; 191 cache-line-size = <64>; 192 cache-sets = <1024>; 193 cache-unified; 194 next-level-cache = <&L3>; 195 }; 196 197 L3: l3-cache { 198 cache-level = <3>; 199 cache-size = <0x800000>; 200 cache-line-size = <64>; 201 cache-sets = <8192>; 202 cache-unified; 203 }; 204 205 pmu { 206 compatible = "arm,cortex-a57-pmu"; 207 interrupts = <0x0 0x7 0x4>, 208 <0x0 0x8 0x4>, 209 <0x0 0x9 0x4>, 210 <0x0 0xa 0x4>, 211 <0x0 0xb 0x4>, 212 <0x0 0xc 0x4>, 213 <0x0 0xd 0x4>, 214 <0x0 0xe 0x4>; 215 interrupt-affinity = <&CPU0>, 216 <&CPU1>, 217 <&CPU2>, 218 <&CPU3>, 219 <&CPU4>, 220 <&CPU5>, 221 <&CPU6>, 222 <&CPU7>; 223 }; 224};