cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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juno-cs-r1r2.dtsi (2432B)

      1// SPDX-License-Identifier: GPL-2.0
      2/ {
      3	funnel@20130000 { /* cssys1 */
      4		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
      5		reg = <0 0x20130000 0 0x1000>;
      6
      7		clocks = <&soc_smc50mhz>;
      8		clock-names = "apb_pclk";
      9		power-domains = <&scpi_devpd 0>;
     10		out-ports {
     11			port {
     12				csys1_funnel_out_port: endpoint {
     13					remote-endpoint = <&etf1_in_port>;
     14				};
     15			};
     16		};
     17		in-ports {
     18			port {
     19				csys1_funnel_in_port0: endpoint {
     20				};
     21			};
     22
     23		};
     24	};
     25
     26	etf_sys1: etf@20140000 { /* etf1 */
     27		compatible = "arm,coresight-tmc", "arm,primecell";
     28		reg = <0 0x20140000 0 0x1000>;
     29
     30		clocks = <&soc_smc50mhz>;
     31		clock-names = "apb_pclk";
     32		power-domains = <&scpi_devpd 0>;
     33		in-ports {
     34			port {
     35				etf1_in_port: endpoint {
     36					remote-endpoint = <&csys1_funnel_out_port>;
     37				};
     38			};
     39		};
     40		out-ports {
     41			port {
     42				etf1_out_port: endpoint {
     43					remote-endpoint = <&csys2_funnel_in_port1>;
     44				};
     45			};
     46		};
     47	};
     48
     49	funnel@20150000 { /* cssys2 */
     50		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
     51		reg = <0 0x20150000 0 0x1000>;
     52
     53		clocks = <&soc_smc50mhz>;
     54		clock-names = "apb_pclk";
     55		power-domains = <&scpi_devpd 0>;
     56		out-ports {
     57			port {
     58				csys2_funnel_out_port: endpoint {
     59					remote-endpoint = <&replicator_in_port0>;
     60				};
     61			};
     62		};
     63
     64		in-ports {
     65			#address-cells = <1>;
     66			#size-cells = <0>;
     67			port@0 {
     68				reg = <0>;
     69				csys2_funnel_in_port0: endpoint {
     70					slave-mode;
     71					remote-endpoint = <&etf0_out_port>;
     72				};
     73			};
     74
     75			port@1 {
     76				reg = <1>;
     77				csys2_funnel_in_port1: endpoint {
     78					slave-mode;
     79					remote-endpoint = <&etf1_out_port>;
     80				};
     81			};
     82
     83		};
     84	};
     85
     86	cti_sys2: cti@20160000 { /* sys_cti_2 */
     87		compatible = "arm,coresight-cti", "arm,primecell";
     88		reg = <0 0x20160000 0 0x1000>;
     89
     90		clocks = <&soc_smc50mhz>;
     91		clock-names = "apb_pclk";
     92		power-domains = <&scpi_devpd 0>;
     93
     94		#address-cells = <1>;
     95		#size-cells = <0>;
     96
     97		trig-conns@0 {
     98			reg = <0>;
     99			arm,trig-in-sigs=<0 1>;
    100			arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
    101			arm,trig-out-sigs=<0 1>;
    102			arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
    103			arm,cs-dev-assoc = <&etf_sys1>;
    104		};
    105
    106		trig-conns@1 {
    107			reg = <1>;
    108			arm,trig-in-sigs=<2 3 4>;
    109			arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
    110			arm,trig-conn-name = "ela_clus_0";
    111		};
    112
    113		trig-conns@2 {
    114			reg = <2>;
    115			arm,trig-in-sigs=<5 6 7>;
    116			arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
    117			arm,trig-conn-name = "ela_clus_1";
    118		};
    119	};
    120};