cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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exynos5433-tm2e.dts (2413B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Samsung Exynos5433 TM2E board device tree source
      4 *
      5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
      6 *
      7 * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
      8 * Samsung Exynos5433 SoC.
      9 */
     10
     11#include "exynos5433-tm2-common.dtsi"
     12
     13/ {
     14	model = "Samsung TM2E board";
     15	compatible = "samsung,tm2e", "samsung,exynos5433";
     16	chassis-type = "handset";
     17};
     18
     19&cmu_disp {
     20	/*
     21	 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
     22	 * clocks properties for DISP CMU for each board to keep them together
     23	 * for easier review and maintenance.
     24	 */
     25	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
     26			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
     27			  <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
     28			  <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
     29			  <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
     30			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
     31			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
     32			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
     33			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
     34			  <&cmu_disp CLK_MOUT_DISP_PLL>,
     35			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
     36			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
     37			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
     38	assigned-clock-parents = <0>, <0>,
     39				 <&cmu_mif CLK_ACLK_DISP_333>,
     40				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
     41				 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
     42				 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
     43				 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
     44				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
     45				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
     46				 <&cmu_disp CLK_FOUT_DISP_PLL>,
     47				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
     48				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
     49				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
     50	assigned-clock-rates = <278000000>, <400000000>;
     51};
     52
     53&dsi {
     54	panel@0 {
     55		compatible = "samsung,s6e3hf2";
     56		reg = <0>;
     57		vdd3-supply = <&ldo27_reg>;
     58		vci-supply = <&ldo28_reg>;
     59		reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
     60		enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
     61	};
     62};
     63
     64&ldo31_reg {
     65	regulator-name = "TSP_VDD_1.8V_AP";
     66	regulator-min-microvolt = <1800000>;
     67	regulator-max-microvolt = <1800000>;
     68};
     69
     70&ldo38_reg {
     71	regulator-name = "VCC_3.3V_MOTOR_AP";
     72	regulator-min-microvolt = <3300000>;
     73	regulator-max-microvolt = <3300000>;
     74};
     75
     76&stmfts {
     77	touchscreen-size-x = <1599>;
     78	touchscreen-size-y = <2559>;
     79	touch-key-connected;
     80	ledvdd-supply = <&ldo33_reg>;
     81};