exynos7885.dtsi (10205B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos7885 SoC device tree source 4 * 5 * Copyright (c) 2021 Samsung Electronics Co., Ltd. 6 * Copyright (c) 2021 Dávid Virág 7 */ 8 9#include <dt-bindings/clock/exynos7885.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7885"; 14 #address-cells = <2>; 15 #size-cells = <1>; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 pinctrl0 = &pinctrl_alive; 21 pinctrl1 = &pinctrl_dispaud; 22 pinctrl2 = &pinctrl_fsys; 23 pinctrl3 = &pinctrl_top; 24 }; 25 26 arm-a53-pmu { 27 compatible = "arm,cortex-a53-pmu"; 28 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 34 interrupt-affinity = <&cpu0>, 35 <&cpu1>, 36 <&cpu2>, 37 <&cpu3>, 38 <&cpu4>, 39 <&cpu5>; 40 }; 41 42 arm-a73-pmu { 43 compatible = "arm,cortex-a73-pmu"; 44 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 46 interrupt-affinity = <&cpu6>, 47 <&cpu7>; 48 }; 49 50 cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 cpu-map { 55 cluster0 { 56 core0 { 57 cpu = <&cpu0>; 58 }; 59 core1 { 60 cpu = <&cpu1>; 61 }; 62 core2 { 63 cpu = <&cpu2>; 64 }; 65 core3 { 66 cpu = <&cpu3>; 67 }; 68 core4 { 69 cpu = <&cpu4>; 70 }; 71 core5 { 72 cpu = <&cpu5>; 73 }; 74 }; 75 76 cluster1 { 77 core0 { 78 cpu = <&cpu6>; 79 }; 80 core1 { 81 cpu = <&cpu7>; 82 }; 83 }; 84 }; 85 86 cpu0: cpu@100 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x100>; 90 enable-method = "psci"; 91 }; 92 93 cpu1: cpu@101 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x101>; 97 enable-method = "psci"; 98 }; 99 100 cpu2: cpu@102 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x102>; 104 enable-method = "psci"; 105 }; 106 107 cpu3: cpu@103 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a53"; 110 reg = <0x103>; 111 enable-method = "psci"; 112 }; 113 114 cpu4: cpu@200 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x200>; 118 enable-method = "psci"; 119 }; 120 121 cpu5: cpu@201 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53"; 124 reg = <0x201>; 125 enable-method = "psci"; 126 }; 127 128 cpu6: cpu@0 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a73"; 131 reg = <0x0>; 132 enable-method = "psci"; 133 }; 134 135 cpu7: cpu@1 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a73"; 138 reg = <0x1>; 139 enable-method = "psci"; 140 }; 141 }; 142 143 psci { 144 compatible = "arm,psci"; 145 method = "smc"; 146 cpu_suspend = <0xc4000001>; 147 cpu_off = <0x84000002>; 148 cpu_on = <0xc4000003>; 149 }; 150 151 timer { 152 compatible = "arm,armv8-timer"; 153 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 158 }; 159 160 fixed-rate-clocks { 161 oscclk: osc-clock { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-output-names = "oscclk"; 165 }; 166 }; 167 168 soc: soc@0 { 169 compatible = "simple-bus"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0x0 0x0 0x0 0x20000000>; 173 174 chipid@10000000 { 175 compatible = "samsung,exynos850-chipid"; 176 reg = <0x10000000 0x24>; 177 }; 178 179 gic: interrupt-controller@12301000 { 180 compatible = "arm,gic-400"; 181 #interrupt-cells = <3>; 182 #address-cells = <0>; 183 interrupt-controller; 184 reg = <0x12301000 0x1000>, 185 <0x12302000 0x2000>, 186 <0x12304000 0x2000>, 187 <0x12306000 0x2000>; 188 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 189 IRQ_TYPE_LEVEL_HIGH)>; 190 }; 191 192 cmu_peri: clock-controller@10010000 { 193 compatible = "samsung,exynos7885-cmu-peri"; 194 reg = <0x10010000 0x8000>; 195 #clock-cells = <1>; 196 197 clocks = <&oscclk>, 198 <&cmu_top CLK_DOUT_PERI_BUS>, 199 <&cmu_top CLK_DOUT_PERI_SPI0>, 200 <&cmu_top CLK_DOUT_PERI_SPI1>, 201 <&cmu_top CLK_DOUT_PERI_UART0>, 202 <&cmu_top CLK_DOUT_PERI_UART1>, 203 <&cmu_top CLK_DOUT_PERI_UART2>, 204 <&cmu_top CLK_DOUT_PERI_USI0>, 205 <&cmu_top CLK_DOUT_PERI_USI1>, 206 <&cmu_top CLK_DOUT_PERI_USI2>; 207 clock-names = "oscclk", 208 "dout_peri_bus", 209 "dout_peri_spi0", 210 "dout_peri_spi1", 211 "dout_peri_uart0", 212 "dout_peri_uart1", 213 "dout_peri_uart2", 214 "dout_peri_usi0", 215 "dout_peri_usi1", 216 "dout_peri_usi2"; 217 }; 218 219 cmu_core: clock-controller@12000000 { 220 compatible = "samsung,exynos7885-cmu-core"; 221 reg = <0x12000000 0x8000>; 222 #clock-cells = <1>; 223 224 clocks = <&oscclk>, 225 <&cmu_top CLK_DOUT_CORE_BUS>, 226 <&cmu_top CLK_DOUT_CORE_CCI>, 227 <&cmu_top CLK_DOUT_CORE_G3D>; 228 clock-names = "oscclk", 229 "dout_core_bus", 230 "dout_core_cci", 231 "dout_core_g3d"; 232 }; 233 234 cmu_top: clock-controller@12060000 { 235 compatible = "samsung,exynos7885-cmu-top"; 236 reg = <0x12060000 0x8000>; 237 #clock-cells = <1>; 238 239 clocks = <&oscclk>; 240 clock-names = "oscclk"; 241 }; 242 243 pinctrl_alive: pinctrl@11cb0000 { 244 compatible = "samsung,exynos7885-pinctrl"; 245 reg = <0x11cb0000 0x1000>; 246 247 wakeup-interrupt-controller { 248 compatible = "samsung,exynos7-wakeup-eint"; 249 interrupt-parent = <&gic>; 250 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 251 }; 252 }; 253 254 pinctrl_fsys: pinctrl@13430000 { 255 compatible = "samsung,exynos7885-pinctrl"; 256 reg = <0x13430000 0x1000>; 257 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 258 }; 259 260 pinctrl_top: pinctrl@139b0000 { 261 compatible = "samsung,exynos7885-pinctrl"; 262 reg = <0x139b0000 0x1000>; 263 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 264 }; 265 266 pinctrl_dispaud: pinctrl@148f0000 { 267 compatible = "samsung,exynos7885-pinctrl"; 268 reg = <0x148f0000 0x1000>; 269 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 270 }; 271 272 pmu_system_controller: system-controller@11c80000 { 273 compatible = "samsung,exynos7-pmu", "syscon"; 274 reg = <0x11c80000 0x10000>; 275 }; 276 277 serial_0: serial@13800000 { 278 compatible = "samsung,exynos5433-uart"; 279 reg = <0x13800000 0x100>; 280 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&uart0_bus>; 283 clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>, 284 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>; 285 clock-names = "uart", "clk_uart_baud0"; 286 samsung,uart-fifosize = <64>; 287 status = "disabled"; 288 }; 289 290 serial_1: serial@13810000 { 291 compatible = "samsung,exynos5433-uart"; 292 reg = <0x13810000 0x100>; 293 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&uart1_bus>; 296 clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>, 297 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>; 298 clock-names = "uart", "clk_uart_baud0"; 299 samsung,uart-fifosize = <256>; 300 status = "disabled"; 301 }; 302 303 serial_2: serial@13820000 { 304 compatible = "samsung,exynos5433-uart"; 305 reg = <0x13820000 0x100>; 306 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&uart2_bus>; 309 clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>, 310 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>; 311 clock-names = "uart", "clk_uart_baud0"; 312 samsung,uart-fifosize = <256>; 313 status = "disabled"; 314 }; 315 316 i2c_0: i2c@13830000 { 317 compatible = "samsung,s3c2440-i2c"; 318 reg = <0x13830000 0x100>; 319 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&i2c0_bus>; 324 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 325 clock-names = "i2c"; 326 status = "disabled"; 327 }; 328 329 i2c_1: i2c@13840000 { 330 compatible = "samsung,s3c2440-i2c"; 331 reg = <0x13840000 0x100>; 332 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&i2c1_bus>; 337 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 338 clock-names = "i2c"; 339 status = "disabled"; 340 }; 341 342 i2c_2: i2c@13850000 { 343 compatible = "samsung,s3c2440-i2c"; 344 reg = <0x13850000 0x100>; 345 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&i2c2_bus>; 350 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 351 clock-names = "i2c"; 352 status = "disabled"; 353 }; 354 355 i2c_3: i2c@13860000 { 356 compatible = "samsung,s3c2440-i2c"; 357 reg = <0x13860000 0x100>; 358 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&i2c3_bus>; 363 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 364 clock-names = "i2c"; 365 status = "disabled"; 366 }; 367 368 i2c_4: i2c@13870000 { 369 compatible = "samsung,s3c2440-i2c"; 370 reg = <0x13870000 0x100>; 371 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&i2c4_bus>; 376 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 377 clock-names = "i2c"; 378 status = "disabled"; 379 }; 380 381 i2c_5: i2c@13880000 { 382 compatible = "samsung,s3c2440-i2c"; 383 reg = <0x13880000 0x100>; 384 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&i2c5_bus>; 389 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 390 clock-names = "i2c"; 391 status = "disabled"; 392 }; 393 394 i2c_6: i2c@13890000 { 395 compatible = "samsung,s3c2440-i2c"; 396 reg = <0x13890000 0x100>; 397 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c6_bus>; 402 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 403 clock-names = "i2c"; 404 status = "disabled"; 405 }; 406 407 i2c_7: i2c@11cd0000 { 408 compatible = "samsung,s3c2440-i2c"; 409 reg = <0x11cd0000 0x100>; 410 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c7_bus>; 415 clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>; 416 clock-names = "i2c"; 417 status = "disabled"; 418 }; 419 }; 420}; 421 422#include "exynos7885-pinctrl.dtsi" 423#include "arm/exynos-syscon-restart.dtsi"