cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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exynos850-e850-96.dts (4347B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * WinLink E850-96 board device tree source
      4 *
      5 * Copyright (C) 2018 Samsung Electronics Co., Ltd.
      6 * Copyright (C) 2021 Linaro Ltd.
      7 *
      8 * Device tree source file for WinLink's E850-96 board which is based on
      9 * Samsung Exynos850 SoC.
     10 */
     11
     12/dts-v1/;
     13
     14#include "exynos850.dtsi"
     15#include <dt-bindings/gpio/gpio.h>
     16#include <dt-bindings/input/input.h>
     17#include <dt-bindings/leds/common.h>
     18
     19/ {
     20	model = "WinLink E850-96 board";
     21	compatible = "winlink,e850-96", "samsung,exynos850";
     22
     23	aliases {
     24		mmc0 = &mmc_0;
     25		serial0 = &serial_0;
     26	};
     27
     28	chosen {
     29		stdout-path = &serial_0;
     30	};
     31
     32	/*
     33	 * RAM: 4 GiB (eMCP):
     34	 *   - 2 GiB at 0x80000000
     35	 *   - 2 GiB at 0x880000000
     36	 *
     37	 * 0xbab00000..0xbfffffff: secure memory (85 MiB).
     38	 */
     39	memory@80000000 {
     40		device_type = "memory";
     41		reg = <0x0 0x80000000 0x3ab00000>,
     42		      <0x0 0xc0000000 0x40000000>,
     43		      <0x8 0x80000000 0x80000000>;
     44	};
     45
     46	gpio-keys {
     47		compatible = "gpio-keys";
     48		pinctrl-names = "default";
     49		pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
     50
     51		volume-down-key {
     52			label = "Volume Down";
     53			linux,code = <KEY_VOLUMEDOWN>;
     54			gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
     55		};
     56
     57		volume-up-key {
     58			label = "Volume Up";
     59			linux,code = <KEY_VOLUMEUP>;
     60			gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
     61		};
     62	};
     63
     64	leds {
     65		compatible = "gpio-leds";
     66
     67		/* HEART_BEAT_LED */
     68		user_led1: led-1 {
     69			label = "yellow:user1";
     70			gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
     71			color = <LED_COLOR_ID_YELLOW>;
     72			function = LED_FUNCTION_HEARTBEAT;
     73			linux,default-trigger = "heartbeat";
     74		};
     75
     76		/* eMMC_LED */
     77		user_led2: led-2 {
     78			label = "yellow:user2";
     79			gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
     80			color = <LED_COLOR_ID_YELLOW>;
     81			linux,default-trigger = "mmc0";
     82		};
     83
     84		/* SD_LED */
     85		user_led3: led-3 {
     86			label = "white:user3";
     87			gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
     88			color = <LED_COLOR_ID_WHITE>;
     89			function = LED_FUNCTION_SD;
     90			linux,default-trigger = "mmc2";
     91		};
     92
     93		/* WIFI_LED */
     94		wlan_active_led: led-4 {
     95			label = "yellow:wlan";
     96			gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
     97			color = <LED_COLOR_ID_YELLOW>;
     98			function = LED_FUNCTION_WLAN;
     99			linux,default-trigger = "phy0tx";
    100			default-state = "off";
    101		};
    102
    103		/* BLUETOOTH_LED */
    104		bt_active_led: led-5 {
    105			label = "blue:bt";
    106			gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
    107			color = <LED_COLOR_ID_BLUE>;
    108			function = LED_FUNCTION_BLUETOOTH;
    109			linux,default-trigger = "hci0rx";
    110			default-state = "off";
    111		};
    112	};
    113
    114	/*
    115	 * RTC clock (XrtcXTI); external, must be 32.768 kHz.
    116	 *
    117	 * TODO: Remove this once RTC clock is implemented properly as part of
    118	 *       PMIC driver.
    119	 */
    120	rtcclk: clock-rtcclk {
    121		compatible = "fixed-clock";
    122		clock-output-names = "rtcclk";
    123		#clock-cells = <0>;
    124		clock-frequency = <32768>;
    125	};
    126};
    127
    128&cmu_hsi {
    129	clocks = <&oscclk>, <&rtcclk>,
    130		 <&cmu_top CLK_DOUT_HSI_BUS>,
    131		 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
    132		 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
    133	clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
    134		      "dout_hsi_mmc_card", "dout_hsi_usb20drd";
    135};
    136
    137&mmc_0 {
    138	status = "okay";
    139	mmc-hs200-1_8v;
    140	mmc-hs400-1_8v;
    141	cap-mmc-highspeed;
    142	non-removable;
    143	mmc-hs400-enhanced-strobe;
    144	card-detect-delay = <200>;
    145	clock-frequency = <800000000>;
    146	bus-width = <8>;
    147	samsung,dw-mshc-ciu-div = <3>;
    148	samsung,dw-mshc-sdr-timing = <0 4>;
    149	samsung,dw-mshc-ddr-timing = <2 4>;
    150	samsung,dw-mshc-hs400-timing = <0 2>;
    151
    152	pinctrl-names = "default";
    153	pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
    154		     &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
    155};
    156
    157&oscclk {
    158	clock-frequency = <26000000>;
    159};
    160
    161&pinctrl_alive {
    162	key_voldown_pins: key-voldown-pins {
    163		samsung,pins = "gpa1-0";
    164		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
    165		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
    166		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
    167	};
    168
    169	key_volup_pins: key-volup-pins {
    170		samsung,pins = "gpa0-7";
    171		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
    172		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
    173		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
    174	};
    175};
    176
    177&rtc {
    178	status = "okay";
    179	clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
    180	clock-names = "rtc", "rtc_src";
    181};
    182
    183&serial_0 {
    184	status = "okay";
    185	pinctrl-names = "default";
    186	pinctrl-0 = <&uart1_pins>;
    187};
    188
    189&usi_uart {
    190	samsung,clkreq-on; /* needed for UART mode */
    191	status = "okay";
    192};
    193
    194&watchdog_cl0 {
    195	status = "okay";
    196};
    197
    198&watchdog_cl1 {
    199	status = "okay";
    200};