exynos850.dtsi (18571B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a55-pmu"; 36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 46 }; 47 48 /* Main system clock (XTCXO); external, must be 26 MHz */ 49 oscclk: clock-oscclk { 50 compatible = "fixed-clock"; 51 clock-output-names = "oscclk"; 52 #clock-cells = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 75 cluster1 { 76 core0 { 77 cpu = <&cpu4>; 78 }; 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 core2 { 83 cpu = <&cpu6>; 84 }; 85 core3 { 86 cpu = <&cpu7>; 87 }; 88 }; 89 }; 90 91 cpu0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 }; 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x1>; 101 enable-method = "psci"; 102 }; 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a55"; 106 reg = <0x2>; 107 enable-method = "psci"; 108 }; 109 cpu3: cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x3>; 113 enable-method = "psci"; 114 }; 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 }; 121 cpu5: cpu@101 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x101>; 125 enable-method = "psci"; 126 }; 127 cpu6: cpu@102 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a55"; 130 reg = <0x102>; 131 enable-method = "psci"; 132 }; 133 cpu7: cpu@103 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a55"; 136 reg = <0x103>; 137 enable-method = "psci"; 138 }; 139 }; 140 141 psci { 142 compatible = "arm,psci-1.0"; 143 method = "smc"; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 149 interrupts = 150 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 154 }; 155 156 soc: soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 ranges = <0x0 0x0 0x0 0x20000000>; 161 162 chipid@10000000 { 163 compatible = "samsung,exynos850-chipid"; 164 reg = <0x10000000 0x100>; 165 }; 166 167 timer@10040000 { 168 compatible = "samsung,exynos850-mct", 169 "samsung,exynos4210-mct"; 170 reg = <0x10040000 0x800>; 171 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 184 clock-names = "fin_pll", "mct"; 185 }; 186 187 gic: interrupt-controller@12a01000 { 188 compatible = "arm,gic-400"; 189 #interrupt-cells = <3>; 190 #address-cells = <0>; 191 reg = <0x12a01000 0x1000>, 192 <0x12a02000 0x2000>, 193 <0x12a04000 0x2000>, 194 <0x12a06000 0x2000>; 195 interrupt-controller; 196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 197 IRQ_TYPE_LEVEL_HIGH)>; 198 }; 199 200 pmu_system_controller: system-controller@11860000 { 201 compatible = "samsung,exynos850-pmu", "syscon"; 202 reg = <0x11860000 0x10000>; 203 clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; 204 205 reboot: syscon-reboot { 206 compatible = "syscon-reboot"; 207 regmap = <&pmu_system_controller>; 208 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 209 mask = <0x2>; /* SWRESET_SYSTEM */ 210 value = <0x2>; /* reset value */ 211 }; 212 }; 213 214 watchdog_cl0: watchdog@10050000 { 215 compatible = "samsung,exynos850-wdt"; 216 reg = <0x10050000 0x100>; 217 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 219 clock-names = "watchdog", "watchdog_src"; 220 samsung,syscon-phandle = <&pmu_system_controller>; 221 samsung,cluster-index = <0>; 222 status = "disabled"; 223 }; 224 225 watchdog_cl1: watchdog@10060000 { 226 compatible = "samsung,exynos850-wdt"; 227 reg = <0x10060000 0x100>; 228 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 230 clock-names = "watchdog", "watchdog_src"; 231 samsung,syscon-phandle = <&pmu_system_controller>; 232 samsung,cluster-index = <1>; 233 status = "disabled"; 234 }; 235 236 cmu_peri: clock-controller@10030000 { 237 compatible = "samsung,exynos850-cmu-peri"; 238 reg = <0x10030000 0x8000>; 239 #clock-cells = <1>; 240 241 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 242 <&cmu_top CLK_DOUT_PERI_UART>, 243 <&cmu_top CLK_DOUT_PERI_IP>; 244 clock-names = "oscclk", "dout_peri_bus", 245 "dout_peri_uart", "dout_peri_ip"; 246 }; 247 248 cmu_apm: clock-controller@11800000 { 249 compatible = "samsung,exynos850-cmu-apm"; 250 reg = <0x11800000 0x8000>; 251 #clock-cells = <1>; 252 253 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 254 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 255 }; 256 257 cmu_cmgp: clock-controller@11c00000 { 258 compatible = "samsung,exynos850-cmu-cmgp"; 259 reg = <0x11c00000 0x8000>; 260 #clock-cells = <1>; 261 262 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 263 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 264 }; 265 266 cmu_core: clock-controller@12000000 { 267 compatible = "samsung,exynos850-cmu-core"; 268 reg = <0x12000000 0x8000>; 269 #clock-cells = <1>; 270 271 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 272 <&cmu_top CLK_DOUT_CORE_CCI>, 273 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 274 <&cmu_top CLK_DOUT_CORE_SSS>; 275 clock-names = "oscclk", "dout_core_bus", 276 "dout_core_cci", "dout_core_mmc_embd", 277 "dout_core_sss"; 278 }; 279 280 cmu_top: clock-controller@120e0000 { 281 compatible = "samsung,exynos850-cmu-top"; 282 reg = <0x120e0000 0x8000>; 283 #clock-cells = <1>; 284 285 clocks = <&oscclk>; 286 clock-names = "oscclk"; 287 }; 288 289 cmu_dpu: clock-controller@13000000 { 290 compatible = "samsung,exynos850-cmu-dpu"; 291 reg = <0x13000000 0x8000>; 292 #clock-cells = <1>; 293 294 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 295 clock-names = "oscclk", "dout_dpu"; 296 }; 297 298 cmu_hsi: clock-controller@13400000 { 299 compatible = "samsung,exynos850-cmu-hsi"; 300 reg = <0x13400000 0x8000>; 301 #clock-cells = <1>; 302 303 clocks = <&oscclk>, 304 <&cmu_top CLK_DOUT_HSI_BUS>, 305 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 306 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 307 clock-names = "oscclk", "dout_hsi_bus", 308 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 309 }; 310 311 pinctrl_alive: pinctrl@11850000 { 312 compatible = "samsung,exynos850-pinctrl"; 313 reg = <0x11850000 0x1000>; 314 315 wakeup-interrupt-controller { 316 compatible = "samsung,exynos850-wakeup-eint"; 317 }; 318 }; 319 320 pinctrl_cmgp: pinctrl@11c30000 { 321 compatible = "samsung,exynos850-pinctrl"; 322 reg = <0x11c30000 0x1000>; 323 324 wakeup-interrupt-controller { 325 compatible = "samsung,exynos850-wakeup-eint"; 326 }; 327 }; 328 329 pinctrl_core: pinctrl@12070000 { 330 compatible = "samsung,exynos850-pinctrl"; 331 reg = <0x12070000 0x1000>; 332 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 333 }; 334 335 pinctrl_hsi: pinctrl@13430000 { 336 compatible = "samsung,exynos850-pinctrl"; 337 reg = <0x13430000 0x1000>; 338 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 339 }; 340 341 pinctrl_peri: pinctrl@139b0000 { 342 compatible = "samsung,exynos850-pinctrl"; 343 reg = <0x139b0000 0x1000>; 344 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 345 }; 346 347 pinctrl_aud: pinctrl@14a60000 { 348 compatible = "samsung,exynos850-pinctrl"; 349 reg = <0x14a60000 0x1000>; 350 }; 351 352 rtc: rtc@11a30000 { 353 compatible = "samsung,s3c6410-rtc"; 354 reg = <0x11a30000 0x100>; 355 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 358 clock-names = "rtc"; 359 status = "disabled"; 360 }; 361 362 mmc_0: mmc@12100000 { 363 compatible = "samsung,exynos7-dw-mshc-smu"; 364 reg = <0x12100000 0x2000>; 365 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 369 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 370 clock-names = "biu", "ciu"; 371 fifo-depth = <0x40>; 372 status = "disabled"; 373 }; 374 375 i2c_0: i2c@13830000 { 376 compatible = "samsung,s3c2440-i2c"; 377 reg = <0x13830000 0x100>; 378 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&i2c0_pins>; 383 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 384 clock-names = "i2c"; 385 status = "disabled"; 386 }; 387 388 i2c_1: i2c@13840000 { 389 compatible = "samsung,s3c2440-i2c"; 390 reg = <0x13840000 0x100>; 391 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&i2c1_pins>; 396 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 397 clock-names = "i2c"; 398 status = "disabled"; 399 }; 400 401 i2c_2: i2c@13850000 { 402 compatible = "samsung,s3c2440-i2c"; 403 reg = <0x13850000 0x100>; 404 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&i2c2_pins>; 409 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 410 clock-names = "i2c"; 411 status = "disabled"; 412 }; 413 414 i2c_3: i2c@13860000 { 415 compatible = "samsung,s3c2440-i2c"; 416 reg = <0x13860000 0x100>; 417 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&i2c3_pins>; 422 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 423 clock-names = "i2c"; 424 status = "disabled"; 425 }; 426 427 i2c_4: i2c@13870000 { 428 compatible = "samsung,s3c2440-i2c"; 429 reg = <0x13870000 0x100>; 430 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&i2c4_pins>; 435 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 436 clock-names = "i2c"; 437 status = "disabled"; 438 }; 439 440 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 441 i2c_5: i2c@13880000 { 442 compatible = "samsung,s3c2440-i2c"; 443 reg = <0x13880000 0x100>; 444 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&i2c5_pins>; 449 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 450 clock-names = "i2c"; 451 status = "disabled"; 452 }; 453 454 /* I2C_6 (also called MOTOR_I2C in TRM) */ 455 i2c_6: i2c@13890000 { 456 compatible = "samsung,s3c2440-i2c"; 457 reg = <0x13890000 0x100>; 458 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&i2c6_pins>; 463 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 464 clock-names = "i2c"; 465 status = "disabled"; 466 }; 467 468 sysreg_peri: syscon@10020000 { 469 compatible = "samsung,exynos850-sysreg", "syscon"; 470 reg = <0x10020000 0x10000>; 471 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 472 }; 473 474 sysreg_cmgp: syscon@11c20000 { 475 compatible = "samsung,exynos850-sysreg", "syscon"; 476 reg = <0x11c20000 0x10000>; 477 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 478 }; 479 480 usi_uart: usi@138200c0 { 481 compatible = "samsung,exynos850-usi"; 482 reg = <0x138200c0 0x20>; 483 samsung,sysreg = <&sysreg_peri 0x1010>; 484 samsung,mode = <USI_V2_UART>; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 ranges; 488 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 489 <&cmu_peri CLK_GOUT_UART_IPCLK>; 490 clock-names = "pclk", "ipclk"; 491 status = "disabled"; 492 493 serial_0: serial@13820000 { 494 compatible = "samsung,exynos850-uart"; 495 reg = <0x13820000 0xc0>; 496 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&uart0_pins>; 499 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 500 <&cmu_peri CLK_GOUT_UART_IPCLK>; 501 clock-names = "uart", "clk_uart_baud0"; 502 status = "disabled"; 503 }; 504 }; 505 506 usi_hsi2c_0: usi@138a00c0 { 507 compatible = "samsung,exynos850-usi"; 508 reg = <0x138a00c0 0x20>; 509 samsung,sysreg = <&sysreg_peri 0x1020>; 510 samsung,mode = <USI_V2_I2C>; 511 #address-cells = <1>; 512 #size-cells = <1>; 513 ranges; 514 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 515 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 516 clock-names = "pclk", "ipclk"; 517 status = "disabled"; 518 519 hsi2c_0: i2c@138a0000 { 520 compatible = "samsung,exynosautov9-hsi2c"; 521 reg = <0x138a0000 0xc0>; 522 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&hsi2c0_pins>; 527 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 528 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 529 clock-names = "hsi2c", "hsi2c_pclk"; 530 status = "disabled"; 531 }; 532 }; 533 534 usi_hsi2c_1: usi@138b00c0 { 535 compatible = "samsung,exynos850-usi"; 536 reg = <0x138b00c0 0x20>; 537 samsung,sysreg = <&sysreg_peri 0x1030>; 538 samsung,mode = <USI_V2_I2C>; 539 #address-cells = <1>; 540 #size-cells = <1>; 541 ranges; 542 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 543 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 544 clock-names = "pclk", "ipclk"; 545 status = "disabled"; 546 547 hsi2c_1: i2c@138b0000 { 548 compatible = "samsung,exynosautov9-hsi2c"; 549 reg = <0x138b0000 0xc0>; 550 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&hsi2c1_pins>; 555 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 556 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 557 clock-names = "hsi2c", "hsi2c_pclk"; 558 status = "disabled"; 559 }; 560 }; 561 562 usi_hsi2c_2: usi@138c00c0 { 563 compatible = "samsung,exynos850-usi"; 564 reg = <0x138c00c0 0x20>; 565 samsung,sysreg = <&sysreg_peri 0x1040>; 566 samsung,mode = <USI_V2_I2C>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 ranges; 570 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 571 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 572 clock-names = "pclk", "ipclk"; 573 status = "disabled"; 574 575 hsi2c_2: i2c@138c0000 { 576 compatible = "samsung,exynosautov9-hsi2c"; 577 reg = <0x138c0000 0xc0>; 578 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&hsi2c2_pins>; 583 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 584 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 585 clock-names = "hsi2c", "hsi2c_pclk"; 586 status = "disabled"; 587 }; 588 }; 589 590 usi_spi_0: usi@139400c0 { 591 compatible = "samsung,exynos850-usi"; 592 reg = <0x139400c0 0x20>; 593 samsung,sysreg = <&sysreg_peri 0x1050>; 594 samsung,mode = <USI_V2_SPI>; 595 #address-cells = <1>; 596 #size-cells = <1>; 597 ranges; 598 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 599 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 600 clock-names = "pclk", "ipclk"; 601 status = "disabled"; 602 }; 603 604 usi_cmgp0: usi@11d000c0 { 605 compatible = "samsung,exynos850-usi"; 606 reg = <0x11d000c0 0x20>; 607 samsung,sysreg = <&sysreg_cmgp 0x2000>; 608 samsung,mode = <USI_V2_I2C>; 609 #address-cells = <1>; 610 #size-cells = <1>; 611 ranges; 612 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 613 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 614 clock-names = "pclk", "ipclk"; 615 status = "disabled"; 616 617 hsi2c_3: i2c@11d00000 { 618 compatible = "samsung,exynosautov9-hsi2c"; 619 reg = <0x11d00000 0xc0>; 620 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&hsi2c3_pins>; 625 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 626 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 627 clock-names = "hsi2c", "hsi2c_pclk"; 628 status = "disabled"; 629 }; 630 631 serial_1: serial@11d00000 { 632 compatible = "samsung,exynos850-uart"; 633 reg = <0x11d00000 0xc0>; 634 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&uart1_single_pins>; 637 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 638 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 639 clock-names = "uart", "clk_uart_baud0"; 640 status = "disabled"; 641 }; 642 }; 643 644 usi_cmgp1: usi@11d200c0 { 645 compatible = "samsung,exynos850-usi"; 646 reg = <0x11d200c0 0x20>; 647 samsung,sysreg = <&sysreg_cmgp 0x2010>; 648 samsung,mode = <USI_V2_I2C>; 649 #address-cells = <1>; 650 #size-cells = <1>; 651 ranges; 652 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 653 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 654 clock-names = "pclk", "ipclk"; 655 status = "disabled"; 656 657 hsi2c_4: i2c@11d20000 { 658 compatible = "samsung,exynosautov9-hsi2c"; 659 reg = <0x11d20000 0xc0>; 660 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&hsi2c4_pins>; 665 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 666 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 667 clock-names = "hsi2c", "hsi2c_pclk"; 668 status = "disabled"; 669 }; 670 671 serial_2: serial@11d20000 { 672 compatible = "samsung,exynos850-uart"; 673 reg = <0x11d20000 0xc0>; 674 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&uart2_single_pins>; 677 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 678 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 679 clock-names = "uart", "clk_uart_baud0"; 680 status = "disabled"; 681 }; 682 }; 683 }; 684}; 685 686#include "exynos850-pinctrl.dtsi"