cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl-ls1043a-qds.dts (2464B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
      4 *
      5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
      6 * Copyright 2018 NXP
      7 *
      8 * Mingkai Hu <Mingkai.hu@freescale.com>
      9 */
     10
     11/dts-v1/;
     12#include "fsl-ls1043a.dtsi"
     13
     14/ {
     15	model = "LS1043A QDS Board";
     16	compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
     17
     18	aliases {
     19		gpio0 = &gpio1;
     20		gpio1 = &gpio2;
     21		gpio2 = &gpio3;
     22		gpio3 = &gpio4;
     23		serial0 = &duart0;
     24		serial1 = &duart1;
     25		serial2 = &duart2;
     26		serial3 = &duart3;
     27	};
     28
     29	chosen {
     30		stdout-path = "serial0:115200n8";
     31	};
     32};
     33
     34&duart0 {
     35	status = "okay";
     36};
     37
     38&duart1 {
     39	status = "okay";
     40};
     41
     42&ifc {
     43	#address-cells = <2>;
     44	#size-cells = <1>;
     45	/* NOR, NAND Flashes and FPGA on board */
     46	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
     47		  0x1 0x0 0x0 0x7e800000 0x00010000
     48		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
     49	status = "okay";
     50
     51	nor@0,0 {
     52		compatible = "cfi-flash";
     53		reg = <0x0 0x0 0x8000000>;
     54		big-endian;
     55		bank-width = <2>;
     56		device-width = <1>;
     57	};
     58
     59	nand@1,0 {
     60		compatible = "fsl,ifc-nand";
     61		reg = <0x1 0x0 0x10000>;
     62	};
     63
     64	fpga: board-control@2,0 {
     65		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
     66		reg = <0x2 0x0 0x0000100>;
     67	};
     68};
     69
     70&i2c0 {
     71	status = "okay";
     72
     73	pca9547@77 {
     74		compatible = "nxp,pca9547";
     75		reg = <0x77>;
     76		#address-cells = <1>;
     77		#size-cells = <0>;
     78
     79		i2c@0 {
     80			#address-cells = <1>;
     81			#size-cells = <0>;
     82			reg = <0x0>;
     83
     84			rtc@68 {
     85				compatible = "dallas,ds3232";
     86				reg = <0x68>;
     87				/* IRQ10_B */
     88				interrupts = <0 150 0x4>;
     89			};
     90		};
     91
     92		i2c@2 {
     93			#address-cells = <1>;
     94			#size-cells = <0>;
     95			reg = <0x2>;
     96
     97			ina220@40 {
     98				compatible = "ti,ina220";
     99				reg = <0x40>;
    100				shunt-resistor = <1000>;
    101			};
    102
    103			ina220@41 {
    104				compatible = "ti,ina220";
    105				reg = <0x41>;
    106				shunt-resistor = <1000>;
    107			};
    108		};
    109
    110		i2c@3 {
    111			#address-cells = <1>;
    112			#size-cells = <0>;
    113			reg = <0x3>;
    114
    115			eeprom@56 {
    116				compatible = "atmel,24c512";
    117				reg = <0x56>;
    118			};
    119
    120			eeprom@57 {
    121				compatible = "atmel,24c512";
    122				reg = <0x57>;
    123			};
    124
    125			temp-sensor@4c {
    126				compatible = "adi,adt7461a";
    127				reg = <0x4c>;
    128			};
    129		};
    130	};
    131};
    132
    133&lpuart0 {
    134	status = "okay";
    135};
    136
    137&qspi {
    138	status = "okay";
    139
    140	qflash0: flash@0 {
    141		compatible = "spansion,m25p80";
    142		#address-cells = <1>;
    143		#size-cells = <1>;
    144		spi-max-frequency = <20000000>;
    145		spi-rx-bus-width = <4>;
    146		spi-tx-bus-width = <4>;
    147		reg = <0>;
    148	};
    149};
    150
    151&usb0 {
    152	status = "okay";
    153};
    154
    155#include "fsl-ls1043-post.dtsi"